MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 371

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
TRLX
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
NOTE: Timing in this table refers to the typical timing only. Consult the electrical characteristics for exact worst-
Additional timing rules not covered in
case timing values. 1/4 clock actually means 0 to 1/4 clock, 1/2 clock means 1/4 to 1/2 clock.
• If SETA = 1, an external TA signal is required to terminate the cycle.
• If TRLX = 1 and SETA = 1, the minimum cycle length = 3 clock cycles (even if
• If TRLX = 1, the number of wait states = 2 * SCY & 2 * BSCY
• If EHTR = 1, an extra (idle) clock cycle is inserted between a read cycle and a
• If LBDIP = 1 (late BDIP assertion), the BDIP pin is asserted only after the number
Access
/
SCY = 0000)
following read cycle to another region, or between a read cycle and a following
write cycle to any region.
of wait states for the first beat in a burst have elapsed. See
TION 9 EXTERNAL BUS INTERFACE
that this function can operate only when the cycle termination is internal, using the
number of wait states programmed in one of the ORx registers
Type
Read
Read
Read
Write
Write
Write
Write
Write
Write
Read
Read
Read
Write
Write
Write
Write
Write
Write
MPC556
ACS
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
Table 10-2 Programming Rules for Strobes Timing
CSNT
X
X
X
X
X
X
0
0
0
1
1
1
0
0
0
1
1
1
1/4 * clock
1/2 * clock
1/4 * clock
1/2 * clock
1/4 * clock
1/2 * clock
(1 + 1/4) *
(1 + 1/2) *
(1 + 1/4) *
(1 + 1/2) *
(1 + 1/4) *
(1 + 1/2) *
Asserted
Address
to CS
clock
clock
clock
clock
clock
clock
0
0
0
0
0
0
MEMORY CONTROLLER
Rev. 15 October 2000
Negated to
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/2 * clock
1/2 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
Add/Data
(1 + 1/2) *
(1 + 1/2) *
Invalid
clock
clock
CS
Table 10-2
as well as
Address to
WE/BE or
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
3/4 * clock
(1 + 3/4) *
(1 + 3/4) *
(1 + 3/4) *
Asserted
3/4 clock
3/4 clock
3/4 clock
(1 + 3/4)
(1 + 3/4)
(1 + 3/4)
clock
clock
clock
clock
clock
clock
OE
include the following:
9.5.4 Burst
Negated to
1/4 * clock
1/4 * clock
1/4 * clock
1/2 * clock
1/2 * clock
1/2 * clock
1/4 * clock
1/4 * clock
1/4 * clock
Add/Data
(1 + 1/2) *
(1 + 1/2) *
(1 + 1/2) *
WE/BE
Invalid
clock
clock
clock
X
X
X
X
X
X
Figure 9-13
Negated to
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
1/4 * clock
Add/Data
Mechanism. Note
Invalid
OE
X
X
X
X
X
X
X
X
X
X
X
X
MOTOROLA
Number of
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 + SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
2 * SCY
Cycles
in
Total
2 +
3 +
3 +
2 +
3 +
3 +
3 +
4 +
4 +
SEC-
10-19