MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 761

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

22.8 Non-IEEE 1149.1-1990 Operation
22.9 Boundary Scan Register
MPC555
USER’S MANUAL
In non-IEEE 1149.1-1990 operation, the IEEE 1149.1-1990 test logic must be kept
transparent to the system logic by forcing and holding the TAP controller into the test-
logic-reset controller state. There are two methods of forcing and holding the control-
ler to this state. The first is to assert the TRST signal, forcing the TAP into the test-
logic-reset controller state. The second is to provide at least five TCK pulses with
TMS held high.
The best approach is to connect a pull down resistor to TRST, or to connect it to
PORESET with a resistor. If bounday scan is required, the JTAG controller should
drive TRST to the negated state (“1” value) following PORESET.
The MPC555 / MPC556 scan chain implementation has a 346-bit boundary scan reg-
ister. This register contains bits for all device signal and clock pins and associated con-
trol signals. The XTAL, EXTAL and XFC pins are associated with analog signals and
are not included in the boundary scan register.
An IEEE-1149.1 compliant boundary scan register has been included on the MPC555
/ MPC556. This 346-bit boundary scan register can be connected between TDI and
TDO when EXTEST or SAMPLE/PRELOAD instructions are selected. This register is
used for capturing signal pin data on the input pins, forcing fixed values on the output
signal pins, and selecting the direction and drive characteristics (a logic value or high
impedance) of the bidirectional and three-state signal pins.
ure 22-8
2. The TCK input is not blocked in low-power stop mode. To consume minimal
3. The TMS, TDI and TRST pins include on-chip pullup resistors. In low-power
/
MPC556
power, the TCK input should be externally connected to VDD or ground, al-
though TCK pin is internally connected to ground.
stop mode, these three pins should remain either unconnected or connected to
VDD to achieve minimal power consumption.
depict the various cell types.
For proper reset of the scan chain test logic, the best approach is to
assert TRST at power on reset (PORESET).
IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
Rev. 15 October 2000
NOTE
Figure 22-5
through
MOTOROLA
Fig-
22-7