MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 383

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.8.5 Dual Mapping Base Register (DMBR)
MPC555
USER’S MANUAL
DMBR — Dual Mapping Base Register
HARD RESET:
Bit(s)
24:27
28:30
MSB
16
23
31
0
0
0
0
*The reset value is a reset configuration word value extracted from the indicated internal data bus lines.
HARD RESET:
17
U
/
1
0
MPC556
Name
EHTR
BSCY
TRLX
SCY
18
U
2
0
Table 10-8 OR0 – OR3 Bit Descriptions (Continued)
Extended hold time on read accesses. This bit, when asserted, inserts an idle clock cycle after a
read access from the current bank and any MPC555 / MPC556 write accesses or read accesses
to a different bank.
0 = Memory controller generates normal timing
1 = Memory controller generates extended hold timing
Cycle length in clocks. This four-bit value represents the number of wait states inserted in the
single cycle, or in the first beat of a burst, when the GPCM handles the external memory access.
Values range from from 0 (0b0000) to 15 (0b1111). This is the main parameter for determining
the length of the cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length is (2 + SCY) x Clocks.
If the user has selected an external TA response for this memory bank (by setting the SETA bit),
then the SCY field is not used.
NOTE: Following a system reset, the SCY bits are set to 0b1111 in OR0.
Burst beats length in clocks. This field determines the number of wait states inserted in all burst
beats except the first, when the GPCM starts handling the external memory access and thus us-
ing SCY[0:3] as the main parameter for determining the length of that cycle.
The total cycle length may vary depending on the settings of other timing attributes.
The total memory access length for the beat is is (1 + BSCY) x Clocks.
If the user has selected an external TA response for this memory bank (by setting the SETA bit)
then BSCY[0:3] are not used.
000 = 0-clock-cycle (1 clock per data beat)
001 = 1-clock-cycle wait states (2 clocks per data beat)
010 = 2-clock-cycle wait states (3 clocks per data beat)
011 = 3-clock-cycle wait states (4 clocks per data beat)
1xx = Reserved
Timing relaxed. This bit, when set, modifies the timing of the signals that control the memory de-
vices during a memory access to this memory region. Relaxed timing multiplies by two the num-
ber of wait states determined by the SCY and BSCY fields. Refer to
Timing Options
0 = Normal timing is generated by the GPCM.
1 = Relaxed timing is generated by the GPCM
Following a system reset, the TRLX bit is set in OR0.
19
U
3
0
BA
20
U
4
0
RESERVED
21
for a full list of the effects of this bit on pins timing.
U
5
0
MEMORY CONTROLLER
Rev. 15 October 2000
22
U
6
0
23
7
0
0
RESERVED
,
24
8
0
0
Description
25
9
0
0
10
26
0
0
AT
11
27
0
0
10.3.5 Summary of GPCM
12
28
1
0
DMCS
13
29
0
0
RESERVED
0x2F C140
MOTOROLA
14
30
0
0
ID31*
10-31
DME
LSB
15
31
0