MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 164

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.13.10.8 Optional Instructions
3.13.10.9 Little-Endian Byte Ordering
3.14 PowerPC Virtual Environment Architecture (VEA)
3.14.1 Atomic Update Primitives
3.14.2 Effect of Operand Placement on Performance
3.14.3 Storage Control Instructions
3.14.4 Instruction Synchronize (isync) Instruction
MPC555
USER’S MANUAL
The following check is done on the stored operand in order to determine whether it is
a denormalized single-precision operand and invoke the floating-point assist interrupt
handler handler:
Refer to RCPU Reference Manual (Floating-Point Assist for Denormalized Operands)
for complete description of handling denormalized floating-point numbers.
No optional instructions are supported.
The load/store unit supports little-endian byte ordering as specified in the UISA. In lit-
tle-endian mode, if an attempt is made to execute an individual scalar unaligned trans-
fer, as well as a multiple or string instruction, an alignment interrupt is taken.
Both the lwarx and stwcx instructions are implemented according to the PowerPC ar-
chitecture requirements. The MPC555 / MPC556 does not provide support for snoop-
ing an external bus activity outside the chip. The provision is made to cancel the
reservation inside the MPC555 / MPC556 by using the CR_B and KR_B input pins.
The load/store unit hardware supports all of the PowerPC load/store instructions. An
optimal performance is obtained for naturally aligned operands. These accesses result
in optimal performance (one bus cycle) for up to 4 bytes size and good performance
(two bus cycles) for double precision floating-point operands. Unaligned operands are
supported in hardware and are broken into a series of aligned transfers. The effect of
operand placement on performance is as stated in the VEA, except for the case of 8-
byte operands. In that case, since the MPC555 / MPC556 uses a 32-bit wide data bus,
the performance is good rather than optimal.
The MPC555 / MPC556 does not implement cache control instructions (icbi, isync,
dcbt, dcbi, dcbf, dcbz, dcbst, and dcbtst) .
The isync instruction causes a reflect which waits for all prior instructions to complete
and then executes the next sequential instruction. Any instruction after an isync will
see all effects of prior instructions.
/
MPC556
(FRS
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
1:11
≠
0) AND (FRS
1:11
≤
896)
MOTOROLA
3-42