MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 483

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.7.2 QSPI RAM
MPC555
USER’S MANUAL
Bit(s)
11:15
0:7
10
8
9
The QSPI contains a 160-byte block of dual-ported static RAM that can be accessed
by both the QSPI and the CPU. Because of this dual access capability, up to two wait
states may be inserted into CPU access time if the QSPI is in operation.
The size and type of access of the QSPI RAM by the CPU affects the QSPI access
time. The QSPI allows byte, half-word, and word accesses. Only word accesses of the
RAM by the CPU are coherent because these accesses are an indivisible operation.
If the CPU makes a coherent access of the QSPI RAM, the QSPI cannot access the
QSPI RAM until the CPU is finished. However, a word or misaligned word access is
not coherent because the CPU must break its access of the QSPI RAM into two parts,
which allows the QSPI to access the QSPI RAM between the two accesses by the
CPU.
The RAM is divided into three segments: receive data RAM, transmit data RAM, and
command data RAM. Receive data is information received from a serial device exter-
nal to the MCU. Transmit data is information stored for transmission to an external de-
vice. Command data defines transfer parameters.
organization.
/
CPTQP
SPCR3
HALTA
MODF
MPC556
Name
SPIF
See bit descriptions in
QSPI finished flag. SPIF is set after execution of the command at the address in ENDQP in
SPCR2. If wraparound mode is enabled (WREN = 1), the SPIF is set, after completion of the
command defined by ENDQP, each time the QSPI cycles through the queue.
0 = QSPI is not finished
1 = QSPI is finished
Mode fault flag. The QSPI asserts MODF when the QSPI is in master mode (MSTR = 1) and the
SS input pin is negated by an external driver. Refer to
0 = Normal operation
1 = Another SPI node requested to become the network SPI master while the QSPI was enabled
Halt acknowledge flag. HALTA is set when the QSPI halts in response to setting the HALT bit in
SPCR3. HALTA is also set when the IMB3 FREEZE signal is asserted, provided the FRZ1 bit in
the QSMCMMCR is set. To prevent undefined operation, the user must not modify any QSPI
control registers or RAM while the QSPI is halted.
If HMIE in SPCR3 is set the QSPI sends interrupt requests to the CPU when HALTA is asserted.
0 = QSPI is not halted.
1 = QSPI is halted
Completed queue pointer. CPTQP points to the last command executed. It is updated when the
current command is complete. When the first command in a queue is executing, CPTQP contains
either the reset value 0x0 or a pointer to the last command completed in the previous queue.
If the QSPI is halted, CPTQP may be used to determine which commands have not been exe-
cuted. The CPTQP may also be used to determine which locations in the receive data segment
of the QSPI RAM contain valid received data.
in master mode (SS input taken low).
QUEUED SERIAL MULTI-CHANNEL MODULE
Table 14-18 SPSR Bit Descriptions
Table
Rev. 15 October 2000
14-17.
Description
14.7.8 Mode Fault
Figure 14-5
for more information.
shows RAM
MOTOROLA
14-21