MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 265

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.3.5 PLL Pins
MPC555
USER’S MANUAL
OSCCLK
The PLL maximum lock time is determined by the input clock to the phase detector.
The PLL locks within 500 input clock cycles.
Whenever power-on reset is asserted, the MF bits are set according to
the DFNH and DFNL bits in SCCR are set to the value of 0 (÷1 and 2), respectively.
The following pins are dedicated to the PLL operation:
• VDDSYN — Drain voltage. This is the V
• VSSSYN — Source voltage. This is the V
• XFC — External filter capacitor. XFC connects to the off-chip capacitor for the
/
The voltage should be well-regulated and the pin should be provided with an ex-
tremely low impedance path to the V
to VSSSYN by a 0.1 µF capacitor located as close as possible to the chip pack-
age.
The pin should be provided with an extremely low impedance path to ground.
VSSSYN should be bypassed to VDDSYN by a 0.1 µF capacitor located as close
as possible to the chip package.
PLL filter. One terminal of the capacitor is connected to XFC, and the other termi-
nal is connected to VDDSYN.
The off-chip capacitor must have the following values:
MPC556
Division Factor
Upon initial system power up and after KAPWR is lost, an external
circuit must assert power on reset (PORESET). If limp mode will be
enabled during power-on reset, PORESET must be asserted for at
least 100,000 cycles of input PLL clock after a valid level has been
reached on the KAPWR supply. If limp mode will be disabled,
PORESET should be asserted for approximately 3 µs after a valid
level has been reached on the KAPWR supply.
DIVF[0:4]
Feedback
Figure 8-3 System PLL Block Diagram
CLOCKS AND POWER CONTROL
Comparator
Phase
Rev. 15 October 2000
Delay
Clock
Down
Up
DD
NOTE
power rail. VDDSYN should be bypassed
DD
SS
Charge
Pump
dedicated to the analog PLL circuits.
dedicated to the analog PLL circuits.
VDDSYN / VSSSYN
Multiplication Factor
XFC
MF[0:11]
VCO
Table
(FREQ
System
Frequency
MOTOROLA
÷2
8-1, and
SYS
÷2
)
8-5