MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 41

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Page
Table
Number
Number
9-3 Data Bus Contents for Write Cycles .................................................................... 9-30
9-4 Priority Between Internal and External Masters over External Bus ..................... 9-34
9-5 Burst Length and Order ....................................................................................... 9-36
9-6 BURST/TSIZE Encoding ..................................................................................... 9-37
9-7 Address Type Pins............................................................................................... 9-37
9-8 Address Types Definition..................................................................................... 9-38
9-9 Termination Signals Protocol............................................................................... 9-47
10-1 Timing Attributes Summary ............................................................................... 10-6
10-2 Programming Rules for Strobes Timing........................................................... 10-19
10-3 Boot Bank Fields Values After Hard Reset...................................................... 10-20
10-4 Write Enable/Byte Enable Signals Function .................................................... 10-21
10-5 Memory Controller Address Map ..................................................................... 10-27
10-6 MSTAT Bit Descriptions.................................................................................. 10-28
10-7 BR0 – BR3 Bit Descriptions............................................................................ 10-29
10-8 OR0 – OR3 Bit Descriptions ........................................................................... 10-30
10-9 DMBR Bit Descriptions ................................................................................... 10-32
10-10 DMOR Bit Descriptions.................................................................................. 10-33
11-1 DMPU Registers ................................................................................................ 11-6
11-2 Reservation Snoop Support............................................................................... 11-9
11-3 L2U_MCR LSHOW Modes ................................................................................ 11-9
11-4 L2U Show Cycle Support Chart....................................................................... 11-12
11-5 L2U (PPC) Register Decode............................................................................ 11-12
11-6 Hex Address For SPR Cycles.......................................................................... 11-13
11-7 L2U_MCR Bit Descriptions ............................................................................. 11-14
11-8 L2U_RBAx Bit Descriptions ............................................................................ 11-14
11-9 L2U_RAx Bit Descriptions .............................................................................. 11-15
11-10 L2U_GRA Bit Descriptions ........................................................................... 11-16
12-1 STOP and HSPEED Bit Functionality................................................................ 12-2
12-2 Bus Cycles and System Clock Cycles ............................................................... 12-3
12-3 ILBS Signal functionality .................................................................................... 12-5
12-4 IRQMUX Functionality ....................................................................................... 12-5
12-5 UIMB Interface Register Map ............................................................................ 12-7
12-6 UMCR Bit Descriptions ..................................................................................... 12-8
12-7 UIPEND Bit Descriptions ................................................................................... 12-9
13-1 Multiplexed Analog Input Channels ................................................................... 13-5
13-2 Analog Input Channels .................................................................................... 13-11
13-3 Queue 1 Priority Assertion............................................................................... 13-15
13-4 QADC64 Clock Programmability ..................................................................... 13-28
13-5 QADC64 Status Flags and Interrupt Sources.................................................. 13-30
13-6 QADC64 Address Map .................................................................................... 13-32
13-7 QADC64MCR Bit Descriptions ....................................................................... 13-33
13-8 QADC64INT Bit Descriptions.......................................................................... 13-34
MPC555 / MPC556
LIST OF TABLES
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
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