MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 267

KIT EVALUATION FOR MPC555

MPC555CME

Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet

Specifications of MPC555CME

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
8.6 MPC555 / MPC556 Internal Clock Signals
MPC555
USER’S MANUAL
GCLK1
System Clock
GCLK2
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
T1
T2
T3
T4
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
The internal clocks generated by the clocks module are shown in
clocks module also generates the CLKOUT and ENGCLK external clock signals. The
PLL synchronizes these signals to each other. The PITRTCLK frequency and source
are specified by the RTDIV and RTSEL bits in the SCCR. When the backup clock is
functioning as the system clock, the backup clock is automatically selected as the time
base clock source and is twice the MPC555 / MPC556 system clock.
Note that GCLK1_50, GCLK2_50, and CLKOUT can have a lower frequency than
GCLK1 and GCLK2. This is to enable the external bus operation at lower frequencies
(controlled by EBDF in the SCCR). GCLK2_50 always rises simultaneously with
/
MPC556
Figure 8-4 MPC555 / MPC556 Clocks
CLOCKS AND POWER CONTROL
Rev. 15 October 2000
Figure
MOTOROLA
8-4. The
8-7

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