MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 156

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.11 Exception Model
3.11.1 Exception Classes
3.11.2 Ordered Exceptions
3.11.3 Unordered Exceptions
MPC555
USER’S MANUAL
For a memory access instruction, if the sum of the effective address and the operand
length exceeds the maximum effective address, the storage operand is considered to
wrap around from the maximum effective address to effective address 0.
Effective address computations for both data and instruction accesses use 32-bit un-
signed binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations.
The PowerPC exception mechanism allows the processor to change to supervisor
state as a result of external signals, errors, or unusual conditions arising in the execu-
tion of instructions. When exceptions occur, information about the state of the proces-
sor is saved to certain registers, and the processor begins execution at an address
(exception vector) predetermined for each exception. Processing of exceptions occurs
in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more
specific condition may be determined by examining a register associated with the ex-
ception — for example, the DAE/source instruction service register (DSISR). Addition-
ally, some exception conditions can be explicitly enabled or disabled by software.
The MPC555 / MPC556 exception classes are shown in
In the MPC555 / MPC556, all exceptions except for reset, debug port non-maskable
interrupts, and machine check exceptions are ordered. Ordered exceptions satisfy the
following criteria:
Unordered exceptions may be reported at any time and are not guaranteed to pre-
serve program state information. The processor can never recover from a reset excep-
tion. It can recover from other unordered exceptions in most cases. However, if a
• Only one exception is reported at a time. If, for example, a single instruction en-
• When the exception is taken, no program state is lost.
/
counters multiple exception conditions, those conditions are encountered se-
quentially. After the exception handler handles an exception, instruction
execution continues until the next exception condition is encountered.
MPC556
Synchronous (ordered, precise)
Table 3-20 MPC555 / MPC556 Exception Classes
Asynchronous, unordered
Asynchronous, ordered
Class
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
Instruction-caused exceptions
External interrupt
Exception Type
Machine check
System reset
Decrementer
Table
3-20.
MOTOROLA
3-34