MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 217

KIT EVALUATION FOR MPC555

MPC555CME

Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet

Specifications of MPC555CME

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
MPC555
USER’S MANUAL
IRQ[0:6]
IRQ[7:31]
IMB3 Interrupts:
If programmed to generate interrupts, the SWT and external pin IRQ[0] always gener-
ate a non-maskable interrupt (NMI) to the RCPU. Notice that the RCPU takes the sys-
tem reset interrupt when an NMI is asserted and the external interrupt for any other
interrupt asserted by the interrupt controller.
Each one of the external pins IRQ[1:7] has its own dedicated assigned priority level.
IRQ[0] is also mapped but should be used only as a status bit indicating that IRQ[0]
was asserted and generated an NMI interrupt. There are eight additional interrupt pri-
Interrupt
Levels
32
IMB3
→Level 0:6
IRQ[0:7]
UIMB
→Level 7
/
MPC556
Figure 6-4 MPC555 / MPC556 Interrupt Structure
SIU
Detect
Edge
SYSTEM CONFIGURATION AND PROTECTION
Change of Lock
Debug
DEC
RTC
PIT
Rev. 15 October 2000
TB
8
8
8
8
8
SWT
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
Level 0
IRQ0
I7
I6
I5
I4
I3
I2
I1
I0
Generate
NMI
IREQ
DEC
Debug
IRQOUT
MOTOROLA
RCPU
NMI
6-9

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