MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 233

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.13.2 SIU Interrupt Registers
6.13.2.1 SIPEND Register
6.13.2.2 SIU Interrupt Mask Register (SIMASK)
MPC555
USER’S MANUAL
SIPEND — SIU Interrupt Pending Register
SIMASK — SIU Interrupt Mask Register
IRM0* LVM0
IRQ0
MSB
MSB
16
0
0
0
0
0
RESET:
RESET:
RESET:
The SIU interrupt controller contains the SIPEND, SIMASK, SIEL, and SIVEC regis-
ters.
Each of the 32 bits in the SIPEND register corresponds to an interrupt request. The
bits associated with internal exceptions indicate, if set, that an interrupt service is re-
quested (if not masked by the corresponding bit in the SIMASK register). Each bit re-
flects the status of the internal requestor device and is cleared when the appropriate
actions are initiated by the software in the device itself. Writing to these bits while they
are not set has no effect.
The bits associated with the IRQ pins have a different behavior depending on the sen-
sitivity defined for them in the SIEL register. When the IRQ is defined as a “level” in-
terrupt the corresponding bit behaves similar to the bits associated with internal
interrupt sources. When the IRQ is defined as an “edge” interrupt and if the corre-
sponding bit is set, it indicates that a falling edge was detected on the line and the bit
can be reset by software by writing a 1 to it.
The SIMASK is a 32-bit read/write register. Each bit corresponds to an interrupt re-
quest bit in the SIPEND register. Setting a bit in this register allows the interrupt re-
quest to reach the RCPU. SIMASK is updated by the software and cleared upon reset.
It is the responsibility of the software to determine which of the interrupt sources are
enabled at a given time.
LVL0
17
/
1
0
0
1
0
MPC556
IRQ1
IRM1
18
2
0
0
2
0
LVM1
LVL1
19
3
0
0
3
0
IRM2
IRQ2
SYSTEM CONFIGURATION AND PROTECTION
20
4
0
0
4
0
LVM2
LVL2
21
5
0
0
5
0
IRQ3
IRM3
Rev. 15 October 2000
22
6
0
0
6
0
LVM3
LVL3
RESERVED
23
7
0
0
7
0
IRQ4
IRM4
24
8
0
0
8
0
LVM4
LVL4
25
9
0
0
9
0
IRQ5
IRM5
10
26
10
0
0
0
LVM5
LVL5
11
27
11
0
0
0
IRM6
IRQ6
12
28
12
0
0
0
LVM6
LVL6
13
29
13
0
0
0
0x2F C010
0x2F C014
MOTOROLA
IRM7
IRQ7
14
30
14
0
0
0
LVM7
LVL7
LSB
15
31
15
6-25
0
0
0