MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 355

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.2 Memory Controller Architecture
MPC555
USER’S MANUAL
From zero to 30 wait states can be programmed with TA generation. Four byte-write
and read-enable signals (WE/BE[0:3]) are available for each byte that is written to
memory. An output enable (OE) signal is provided to eliminate external glue logic. A
memory transfer start (MTS) strobe permits one master on a bus to access external
memory through the chip selects on another.
The memory controller functionality allows MPC555 / MPC556-based systems to be
built with little or no glue logic. A minimal system using no glue logic is shown in
10-3. In this example CS[0] is used for the 16-bit boot EPROM and CS[1] is used for
the 32-bit SRAM. The WE/BE[0:3] signals are used both to program the EPROM and
to enable write access to various bytes in the RAM.
The memory controller consists of a basic machine that handles the memory access
cycle: the general-purpose chip-select machine (GPCM).
When a new access to external memory is requested by any of the internal masters,
the address of the transfer (with 17 bits having mask) and the address type (with 3 bits
having mask) are compared to each one of the valid banks defined in the memory con-
troller. Refer to
/
MPC555 / MPC556
MPC556
Figure 10-3 MPC555 / MPC556 Simple System Configuration
WE/BE[0:3]
Figure
Address
CS[0]
CS[1]
Data
OE
10-4.
MEMORY CONTROLLER
Rev. 15 October 2000
[0:31]
[0:15]
Address
CE
CE
OE
OE
WE/BE[0:1]
DATA[0:15]
Address
CE
WE/BE[0:3]
W
Data
OE
EPROM
SRAM
MOTOROLA
Figure
10-3