MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 485

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CR[0:F] — Command RAM
14.7.3 QSPI Pins
MPC555
USER’S MANUAL
Bit(s)
NOTES:
4:7
0
1
2
3
A maximum of 32 commands can be in the queue. These bytes are assigned an ad-
dress from 0x00 to 0x1F. Queue execution by the QSPI proceeds from the address in
NEWQP through the address in ENDQP. (Both of these fields are in SPCR2.)
CONT
CONT
1. The PCS[0] bit represents the dual-function PCS[0]/
Refer to
Seven pins are associated with the QSPI. When not needed by the QSPI, they can be
configured for general-purpose I/O.
functions. Register DDRQS determines whether the pins are designated as input or
output. The user must initialize DDRQS for the QSPI to function correctly.
—
7
/
PCS[3:0]
BITSE
MPC556
CONT
Name
DSCK
DT
14.7.5 Master Mode Operation
BITSE
BITSE
—
Command Control
6
Continue
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete.
Bits per transfer enable
0 = Eight bits
1 = Number of bits set in BITS field of SPCR0.
Delay after transfer
0 = Delay after transfer is 17 ÷ F
1 = SPCR1 DTL[7:0] specifies delay after transfer PCS valid to SCK.
PCS to SCK Delay
0 = PCS valid to SCK delay is one-half SCK.
1 = SPCR1 DSCKL[6:0] specifies delay from PCS valid to SCK.
Peripheral chip selects. Use peripheral chip-select bits to select an external device for serial data
transfer. More than one peripheral chip select may be activated at a time, and more than one
peripheral chip can be connected to each PCS pin, provided proper fanout is observed. PCS[0]
shares a pin with the slave select (SS) signal, which initiates slave mode serial transfer. If SS is
taken low when the QSPI is in master mode, a mode fault occurs.
Table 14-19 Command RAM Bit Descriptions
QUEUED SERIAL MULTI-CHANNEL MODULE
DT
DT
—
5
Rev. 15 October 2000
DSCK
DSCK
—
4
Table 14-20
SYS
.
SS
for more information on the command RAM.
.
PCS3
PCS3
Description
—
3
identifies the QSPI pins and their
PCS2
PCS2
Peripheral Chip Select
—
2
0x30 51C0 – 0x30 51DF
PCS1
PCS1
—
1
MOTOROLA
PCS0
PCS0
—
0
14-23
1
1