MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 137

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.7.4 Condition Register (CR)
MPC555
USER’S MANUAL
30–31
Bit(s)
21
22
23
24
25
26
27
28
29
Table 3-6
The condition register (CR) is a 32-bit register that reflects the result of certain opera-
tions and provides a mechanism for testing and branching. The bits in the CR are
grouped into eight 4-bit fields, CR0 to CR7.
VXSQRT
/
VXSOFT
VXCVI
Name
MPC556
OE
UE
RN
VE
ZE
XE
NI
illustrates the floating-point result flags that correspond to FPSCR[15:19].
Floating-point invalid operation exception for software request. This bit can be altered only by the
mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions. The purpose of VXSOFT is to allow soft-
ware to cause an invalid operation condition for a condition that is not necessarily associated with
the execution of a floating-point instruction. For example, it might be set by a program that com-
putes a square root if the source operand is negative. This is a sticky bit.
Floating-point invalid operation exception for invalid square root. This is a sticky bit. This guar-
antees that software can simulate fsqrt and frsqrte, and to provide a consistent interface to han-
dle exceptions caused by square-root operations.
Floating-point invalid operation exception for invalid integer convert. This is a sticky bit.
Floating-point invalid operation exception enable.
Floating-point overflow exception enable.
Floating-point underflow exception enable. This bit should not be used to determine whether de-
normalization should be performed on floating-point stores.
Floating-point zero divide exception enable.
Floating-point inexact exception enable.
Non-IEEE mode bit.
Floating-point rounding control.
00Round to nearest
01Round toward zero
10Round toward +infinity
11Round toward -infinity
Table 3-6 Floating-Point Result Flags in FPSCR
Table 3-5 FPSCR Bit Descriptions (Continued)
Result Flags
(Bits 15–19)
C<>=?
10001
01001
01000
11000
10010
00010
10100
00100
00101
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
– Denormalized number
+ Denormalized number
– Normalized number
+ Normalized number
Result value class
Quiet NaN
– Infinity
+ Infinity
Description
– Zero
+ Zero
MOTOROLA
3-15