MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 384

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.8.6 Dual-Mapping Option Register
MPC555
USER’S MANUAL
DMOR — Dual-Mapping Option Register
Bit(s)
10:12
13:27
28:30
MSB
1:6
7:9
16
31
0
0
0
0
0
RESET:
RESET:
*It is recommended that this field would hold values that are the power of 2 minus 1 (e.g., - 2
17
/
1
0
0
MPC556
DMCS
Name
DME
BA
AT
—
—
—
18
2
0
0
Reserved
Base address. The base address field is compared (along with the address type field) to the
address of the address bus to determine whether an address should be dual-mapped by one
of the memory banks controlled by the memory controller. These bits are used in conjunction
with the AM[11:16] bits in the OR.
Bit 10: is cleared at reset. That way, the default range for the dual mapping is 2 Mbytes. Note
that by setting this bit, the range becomes 4 Mbyte, which includes memory space beyond the
flash EEPROM memory.
Reserved
Address type. This field can be used to specify that accesses involving the memory bank are
limited to a certain address space type. These bits are used in conjunction with the ATM bits
in the OR. The default value at reset is to map data only. For a full definition of address types,
refer to
Reserved
Dual-mapping chip select. This field determines which chip-select pin is assigned for dual
mapping.
000 = CS[0]
001 = CS[1]
010 = CS[2]
011 = CS[3]
1xx = Reserved
Dual mapping enabled. This bit indicates that the contents of the dual-mapping registers and
associated base and option registers are valid and enables the dual-mapping operation. The
default value at reset comes from the internal data bus that reflects the reset configuration
word. See
0 = Dual mapping is not active
1 = Dual mapping is active
19
3
0
0
AM
*
20
9.5.7.6 Address
4
0
0
Table 10-9 DMBR Bit Descriptions
10.6 Dual Mapping of the Internal Flash EEPROM Array
21
5
0
0
MEMORY CONTROLLER
Rev. 15 October 2000
22
6
0
0
Types.
RESERVED
23
7
0
0
RESERVED
,
24
8
0
0
Description
25
9
0
0
10
26
0
0
ATM
11
27
0
0
12
28
1
0
for more information.
3
13
29
- 1 = 7 [0b111]).
0
0
RESERVED
0x2F C144
MOTOROLA
14
30
0
0
10-32
LSB
15
31
0
0