MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 362

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.3.3 Relaxed Timing Examples
MPC555
USER’S MANUAL
The TRLX field is provided for memory systems that need a more relaxed timing be-
tween signals. When TRLX is set and ACS = 0b00, the memory controller inserts an
additional cycle between address and strobes (CS line and WE/OE).
When TRLX and CSNT are both set in a write to memory, the strobe lines (WE/BE[0:3]
and CS, if ACS = 0b00) are negated one clock earlier than in the regular case.
Note that in the case of a bank selected to work with external transfer acknowledge
(SETA = 1) and TRLX = 1, the memory controller does not support external devices
providing TA to complete the transfer with zero wait states. The minimum access du-
ration in this case equals three clock cycles.
Figure 10-9
• Strobes (OE and CS) assertion time is delayed one clock relative to address
• Strobe (CS) is further delayed (half-clock) relative to address due to ACS field be-
• Total cycle length = 5, is determined as follows:
/
(TRLX bit set effect).
ing set to 11.
— Two clocks for basic cycle
— SCY = 1 determines 1 wait state, which is multiplied by two due to TRLX being
— Extra clock is added due to TRLX effect on the strobes.
MPC556
set.
shows a read access with relaxed timing. Note the following:
MEMORY CONTROLLER
Rev. 15 October 2000
MOTOROLA
10-10