MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 751

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.7.12 Debug Enable Register (DER)
MPC555
USER’S MANUAL
DER — Debug Enable Register
Bit(s)
SERV
Bit(s)
RE-
ED
16
0:1
4:5
28
29
30
31
0
0
0
0
1
2
3
RESET:
RESET:
This register enables the user to selectively mask the events that may cause the pro-
cessor to enter into debug mode.
RSTE
SEEE
17
/
1
0
0
CHSTPE
Name
EBRK
MPC556
LBRK
IBRK
MCEE
DPI
Name
RSTE
—
—
CHST
SERV
RE-
PE
ED
18
2
1
0
L-bus breakpoint exception bit. This bit is set as a result of the assertion of a load/store break-
point. Results in debug mode entry if debug mode is enabled and the corresponding enable bit
is set.
I-bus breakpoint exception bit. This bit is set as a result of the assertion of an Instruction break-
point. Results in debug mode entry if debug mode is enabled and the corresponding enable bit
is set.
External breakpoint exception bit. Set when an external breakpoint is asserted (by an on-chip
IMB or L-bus module, or by an external device or development system through the development
port). This bit is set as a result of the assertion of an external breakpoint. Results in debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
Development port interrupt bit. Set by the development port as a result of a debug station non-
maskable request or when debug mode is entered immediately out of reset.
MCEE
BERE
ITL-
Reserved
Reset enable
0 = Debug entry is disabled (reset value)
1 = Debug entry is enabled
Checkstop enable bit
0 = Debug mode entry disabled
1 = Debug mode entry enabled (reset value)
Machine check exception enable bit
0 = Debug mode entry disabled (reset value)
1 = Debug mode entry enabled
Reserved
19
3
0
0
Table 21-27 ECR Bit Descriptions (Continued)
SERV
RESERVED
RE-
ED
20
4
0
0
Table 21-28 DER Bit Descriptions
BERE
DTL-
21
5
0
0
DEVELOPMENT SUPPORT
EXTIE ALEE PREE
Rev. 15 October 2000
22
6
0
0
23
7
0
0
RESERVED
24
8
0
0
Description
Description
FPU-
VEE
25
9
0
0
CEE
DE-
10
26
0
0
RESERVED
11
27
0
0
LBRK
12
28
E
0
1
IBRKE
SEE
SY-
13
29
0
1
MOTOROLA
EBRK
SPR 149
TRE
14
30
E
1
1
FPAS
DPIE
21-55
15
31
E
0
1