MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 261

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.1 Overview
MPC555 / MPC556
USER’S MANUAL
The main timing reference for the MPC555 / MPC556 can monitor any of the following:
The system operating frequency is generated through a programmable phase-locked
loop, the system PLL (SPLL). The SPLL is programmable in integer multiples of the
input oscillator frequency to generate the internal (VCO/2) operating frequency. A pre-
divider before the SPLL enables the user to divide the high frequency crystal oscillator.
The SPLL VCO is twice the system frequency. The internal operating SPLL frequency
should be at least 30 MHz. It can be divided by a power-of-two divider to generate the
system operating frequencies.
In addition to the system clock, the clocks submodule provides the following:
The oscillator, TB, DEC, RTC, and the PIT are powered from the keep alive power
supply (KAPWR) pin. This allows the counters to continue to count (increment/decre-
ment) at the oscillator frequency even when the main power to the MCU is off. While
the power is off, the PIT may be used to signal to the power supply IC to enable power
to the system at specific intervals. This is the power-down wake-up feature. When the
chip is not in power-down low-power mode, the KAPWR is powered to the same volt-
age value as the voltage of the I/O buffers and logic.
The MPC555 / MPC556 clock module consists of the main crystal oscillator (OSCM),
the SPLL, the low-power divider, the clock generator, the system low-power control
block, and the limp mode control block. The clock module receives control bits from
the system clock control register (SCCR), change of lock interrupt register (COLIR),
the low-power and reset-control register (PLPRCR), and the PLL.
All of the MPC555 peripherals on the IMB bus derive its clock timing from the UIMB
module. The UIMB runs on the main system clock, but can divide the system frequen-
cy in half. See
Figure 8-1
• A crystal with a frequency of four MHz or 20 MHz
• An external frequency source with a frequency of 4 MHz
• An external frequency source at the system frequency
• TMBCLK to the time base (TB) and decrementer (DEC)
• PITRTCLK to the periodic interrupt timer (PIT) and real-time clock (RTC)
illustrates the functional block diagram of the clock unit.
12.3 Clock
CLOCKS AND POWER CONTROL
CLOCKS AND POWER CONTROL
Module.
Rev. 15 October 2000
SECTION 8
MOTOROLA
8-1