MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 387

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11.1 General Features
11.2 DMPU Features
MPC555 / MPC556
USER’S MANUAL
The L-bus to U-bus interface unit (L2U) provides an interface between the load/store
bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory
protection unit (DMPU), which provides protection for data memory accesses.
The L2U is bi-directional. It allows load/store accesses not intended for the L-bus data
RAM to go to the U-bus. It also allows code execution from the L-bus data RAM and
read/write accesses from the U-bus to the L-bus.
The L2U directs bus traffic between the L-bus and the U-bus. When transactions start
concurrently on both buses, the L2U interface arbitrates to select which transaction is
handled. The top priority is assigned to U-bus to L-bus accesses; lower priority is as-
signed to the load/store accesses by the RCPU.
• Non-pipelined master and slave on U-bus
• Non-pipelined master and slave on the L-bus
• Generates module selects for L-bus memory-mapped resources within a pro-
• Programmable data memory protection unit (DMPU)
• L-bus and U-bus snoop logic for PowerPC reservation protocol
• L2U does not support dual mapping of L-bus or IMB3 space
• Show cycles for RCPU accesses to the SRAM (none, all, writes)
• Supports four memory regions whose base address and size can be programmed
• Each of the four regions supports the following attributes:
grammable, contiguous block of storage
— Does not start two back-to-back accesses on the U-bus
— Supports the U-bus pipelining by starting a cycle on the U-bus when U-bus
— Does not accept back-to-back accesses from the U-bus master
— Protection for SRAM accesses from the U-bus side (all accesses to the SRAM
— Available sizes are 4 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128
— Region must start on the specified region size boundary
— Overlap between regions is allowed
pipe depth is zero or one
from the U-bus side are blocked once the SRAM protection bit is set)
Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, and
16 Mbytes
• Access protection: user or supervisor
• Guarded attribute: speculative or non-speculative
• Enable/disable option
• Read only option
L-BUS TO U-BUS INTERFACE (L2U)
L-BUS TO U-BUS INTERFACE (L2U)
Rev. 15 October 2000
SECTION 11
MOTOROLA
11-1