MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 169

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.15.4.9 Floating-Point Unavailable Interrupt
3.15.4.10 Trace Interrupt
3.15.4.11 Floating-Point Assist Interrupt
MPC555
USER’S MANUAL
The floating-point unavailable interrupt is generated by the MPC555 / MPC556 core
as defined in the OEA.
A trace interrupt occurs if MSR
pleted or MSR
not occur after an instruction that caused an interrupt (for instance, sc). A monitor/de-
bugger software must change the vectors of other possible interrupt addresses to sin-
gle-step such instructions. If this is unacceptable, other debug features can be used.
Refer to
ing registers are set:
Execution resumes at offset 0x00D00 from the base address indicated by MSR
A floating-point assist interrupt occurs in the following cases:
The following registers are set:
Execution resumes at offset 0x00E00 from the base address indicated by MSR
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
• When a floating-point exception condition is detected, the corresponding floating-
• When an intermediate result is detected and the floating-point underflow excep-
• In some cases when at least one of the source operands is denormalized.
/
point enable bit in the FPSCR (floating-point status and control register) is set (ex-
ception enabled) and ((MSR
MSR
rfi, the floating-point assist interrupt handler is not invoked.
tion is disabled (FPSCR
MPC556
Register Name
SECTION 21 DEVELOPMENT SUPPORT
FE1
) and FPSCR
BE
= 1 and a branch is completed. Notice that the trace interrupt does
FEX
CENTRAL PROCESSING UNIT
10:15
Other
Other
UE
Bits
ME
1:4
LE
IP
SE
) is set as a result of move to FPSCR, move to MSR or
Rev. 15 October 2000
= 0)
= 1 and any instruction except rfi is successfully com-
FE0
Set to the effective address of the instruction following the ex-
ecuted instruction
Set to 0
Set to 0
Loaded from bits 16:31 of MSR. In the current implementa-
tion, Bit 30 of the SRR1 is never cleared, except by loading a
zero value from MSR
No change
No change
Bit is copied from ILE
Set to 0
| MSR
FE1
) = 1). Note that when ((MSR
RI
for more information. The follow-
Description
MOTOROLA
IP.
IP
FE0
.
3-47
|