MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 168

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.15.4.4 Instruction Storage Interrupt
3.15.4.5 Alignment Interrupt
3.15.4.6 Floating-Point Enabled Exception Type Program Interrupt
3.15.4.7 Illegal Instruction Type Program Interrupt
3.15.4.8 Privileged Instruction Type Program interrupt
MPC555
USER’S MANUAL
An instruction storage interrupt is never generated by the hardware. The software may
branch to this location as a result of an implementation-specific instruction storage pro-
tection error interrupt.
An alignment exception occurs as a result of one of the following conditions:
A floating-point enabled exception type program interrupt is generated if ((MSR
MSR
instruction or the execution of the rfi instruction. A floating-point enabled exception
type program interrupt is not generated by floating-point arithmetic instructions. In-
stead if ((MSR
generated.
An illegal instruction type program interrupt is not generated by the MPC555 /
MPC556. An implementation dependent software emulation interrupt is generated in-
stead.
A privileged instruction type program interrupt is generated for an on-core valid SPR
field or any SPR encoded as an external to the core special register if SPR
MSR
Data/Storage Interrupt Status
Data Address Register (DAR)
• The operand of a floating-point load or store is not word aligned.
• The operand of load/store multiple is not word aligned.
• The operand of lwarx or stwcx is not word aligned.
• The operand of load/store individual scalar instruction is not naturally aligned
• An attempt to execute multiple/string instruction is made when MSR
/
when MSR
FE1
PR
MPC556
Register (DSISR)
Register Name
= 1, as well as an attempt to execute privileged instruction when MSR
) &FPSCR
FE0
LE
= 1.
| MSR
FEX
) is set as a result of move to FPSCR instruction, move to MSR
FE1
CENTRAL PROCESSING UNIT
) &FPSCR
15:16
18:21
22:31
Bits
0:14
17
Rev. 15 October 2000
Set to 0
Set to bits 29:30 of the instruction if X-form and to 0b00 if D-
form
Set to Bit 25 of the instruction if X-form and to Bit 5 if D-form
Set to bits 21:24 of the instruction if X-form and to bits 1:4 if
D-form
Set to bits 6:15 of the instruction
Set to the effective address of the data access that caused
the interrupt
FEX
) is set, the floating-point assist interrupt is
Description
LE
MOTOROLA
= 1.
0
= 1 and
PR
FE0
= 1.
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