MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 231

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.13.1.3 External Master Control Register (EMCR)
MPC555
USER’S MANUAL
EMCR — External Master Control Register
Bit(s)
16:19
21:22
24:27
28:30
MSB
8:15
0:7
20
23
31
0
0
RESET:
The external master control register selects the external master modes and deter-
mines the internal bus attributes for external-to-internal accesses.
/
1
0
MASKNUM
PARTNUM
MPC556
Name
CLES
FLEN
ISB
—
—
—
—
2
0
3
0
This read-only field is mask programmed with a code corresponding to the part number of
the part on which the SIU is located. It is intended to help factory test and user code which
is sensitive to part changes. This changes when the part number changes. For example, it
would change if any new module is added, if the size of any memory module is changed. It
would not change if the part is changed to fix a bug in an existing module. The MPC555 /
MPC556 chip has an ID of 0x30.
This read-only field is mask programmed with a code corresponding to the mask number of
the part. It is intended to help factory test and user code which is sensitive to part changes.
Reserved
Flash enable is a read-write bit. The default state of FLEN is negated, meaning that the boot
is performed from external memory. This bit can be set at reset by the reset configuration
word.
0 = On-chip flash memory is disabled, and all internal cycles to the allocated flash address
1 = On-chip flash memory is enabled
Reserved
Core little-endian swap
0 = Little-endian swap logic in the EBI is not activated for RCPU accesses after reset
1 = Little-endian swap logic in the EBI is activated for RCPU accesses after reset
Reserved
This read-write field defines the base address of the internal memory space. The initial value
of this field can be configured at reset to one of eight addresses, and then can be changed
to any value by software. Internal base addresses are as follows:
000 = 0x0000 0000
001 = 0x0040 0000
010 = 0x0080 0000
011 = 0x00C0 0000
100 = 0x0100 0000
101 = 0x0140 0000
110 = 0x0180 0000
111 = 0x01C0 0000
Reserved
space are mapped to external memory
SYSTEM CONFIGURATION AND PROTECTION
4
0
Table 6-11 IMMR Bit Descriptions
5
0
Rev. 15 October 2000
6
0
RESERVED
7
0
8
0
Description
9
0
10
0
11
0
12
0
13
0
0x2F C030
MOTOROLA
14
0
15
6-23
0