MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 228

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
NOTES:
Bit(s)
13:14
17:18
20:21
22:23
25:31
9:10
1:3
4:7
11
12
15
16
19
24
0
8
1. WE/BE is selected per memory region by WEBS in the approprite BR register in the memory controller.
/
MPC556
DSHW
ATWC
DBGC
MLRC
MTSC
Name
EARB
EARP
DBPC
RCTX
GPC
DLK
SC
—
—
—
—
External arbitration
0 = Internal arbitration is performed
1 = External arbitration is assumed
External arbitration request priority. This field defines the priority of an external master’s arbitra-
tion request. This field is valid when EARB is cleared. Refer to
details.
Reserved
Data show cycles. This bit selects the show cycle mode to be applied to U-bus data cycles (data
cycles to IMB modules and flash EEPROM). This field is locked by the DLK bit. Note that instruc-
tion show cycles are programmed in the ICTRL and L-bus data show cycles (to SRAM) are pro-
grammed in the L2UMCR.
0 = Disable show cycles for all internal data cycles
1 = Show address and data of all internal data cycles
Debug pins configuration. Refer to
Debug port pins configuration. Refer to
Address write type enable configuration. This bit configures the pins to function as byte write en-
ables or address types for debugging purposes.
0 = WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]
1 = WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3]
This bit configures the pins as shown in
Debug register lock
0 = Normal operation
1 = SIUMCR is locked and can be written only in test mode or when the internal freeze signal is
Reserved
Single-chip select. This field configures the functionality of the address and data buses. Chang-
ing the SC field while external accesses are performed is not supported. Refer to
Reset configuration/timer expired. During reset the RSTCONF/TEXP pin functions as
RSTCONF. After reset the pin can be configured to function as TEXP, the timer expired signal
that supports the low-power modes.
0 = RSTCONF/TEXP functions as RSTCONF
1 = RSTCONF/TEXP functions as TEXP
Multi-level reservation control. This field selects between the functionality of the reservation logic
and IRQ pins, refer to
Reserved
Memory transfer start control.
0 = IRQ[2]/CR/SGPIOC[2]/MTS functions according to the MLRC bits setting
1 = IRQ[2]/CR/SGPIOC[2]/MTS functions as MTS
Reserved
asserted.
SYSTEM CONFIGURATION AND PROTECTION
Table 6-5 SIUMCR Bit Descriptions
Table
Rev. 15 October 2000
6-10.
Table
Table
Table
Description
6-6.
6-7.
6-8.
1
9.5.6.4 Internal Bus Arbiter
MOTOROLA
Table
6-9.
6-20
for