MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 643

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

18.1 Features
MPC555 / MPC556
USER’S MANUAL
The dual-port RAM module with TPU microcode storage support (DPTRAM) consists
of a control register block and a 6-Kbyte array of static RAM, which can be used either
as a microcode storage for TPU or as a general-purpose memory.
The DPTRAM module acts as a common memory on the IMB3 and allows the transfer
of data to the two TPU3 modules. Therefore, the DPTRAM interface includes an IMB3
bus interface and two TPU3 interfaces. When the RAM is being used in microcode
mode, the array is only accessible to the TPU3 via a separate local bus, and not via
the IMB3.
The dual-port TPU3 RAM (DPTRAM) is intended to serve as fast, two-clock access,
general-purpose RAM memory for the MCU. When used as general-purpose RAM,
this module is accessed via the MCU’s internal bus.
The DPTRAM module is powered by VDDL in normal operation. The entire array may
be used as standby RAM if standby power is supplied via the VDDSRAM pin of the
MCU. VDDSRAM must be supplied by an external source.
The DPTRAM may also be used as the microcode control store for up to two TPU3
modules when placed in a special emulation mode. In this mode the DPTRAM array
may only be accessed by either or both of the TPU3 units simultaneously via separate
emulation buses, and not via the IMB3.
The DPTRAM contains a multiple input signature calculator (MISC) in order to provide
RAM data corruption checking. The MISC reads each RAM address and generates a
32-bit data-dependent signature. This signature can then be checked by the host.
The DPTRAM supports soft defects detection (SDD).
• Six Kbytes of static RAM
• Only accessible by the CPU if neither TPU3 is in emulation mode
• Low-power stop operation
• TPU microcode mode
— Entered by setting the STOP bit in the DPTMCR
— Applies only to IMB3 accesses and not to accesses from either TPU3 interface
— The DPTRAM array acts as a microcode storage for the TPU module. This
provides a means executing TPU code out of DPTRAM instead of program-
ming it in the TPU ROM.
The RCPU can not perform instruction fetches from any module on
the IMB (including the DPTRAM). Only data accesses are permitted.
DUAL-PORT TPU RAM (DPTRAM)
DUAL-PORT TPU RAM (DPTRAM)
Rev. 15 October 2000
SECTION 18
NOTE
MOTOROLA
18-1