MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 160

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.13 PowerPC User Instruction Set Architecture (UISA)
3.13.1 Computation Modes
3.13.2 Reserved Fields
3.13.3 Classes of Instructions
MPC555
USER’S MANUAL
The core of the MPC555 / MPC556 is a 32-bit implementation of the PowerPC archi-
tecture. Any reference in the PowerPC Architecture Books (UISA, VEA, OEA) regard-
ing 64-bit implementations are not supported by the core. All registers except the
floating-point registers are 32 bits wide.
Reserved fields in instructions are described under the specific instruction definition
sections. Unless otherwise stated in the specific instruction description, fields marked
“I”, “II” and “III” in the instruction are discarded by the core decoding. Thus, this type
of invalid form instructions yield results of the defined instructions with the appropriate
field zero.
In most cases, the reserved fields in registers are ignored on write and return zeros for
them on read on any control register implemented by the MPC555 / MPC556. Excep-
tion to this rule are bits 16:23 of the fixed-point exception cause register (XER) and the
reserved bits of the machine state register (MSR), which are set by the source value
on write and return the value last set for it on read.
Non-optional instructions are implemented by the hardware. Optional instructions are
executed by implementation-dependent code and any attempt to execute one of these
commands causes the MPC555 / MPC556 to take the implementation-dependent soft-
ware emulation interrupt (offset 0x01000 of the vector table).
Illegal and reserved instruction class instructions are supported by implementation-
dependent code and, thus, the MPC555 / MPC556 hardware generates the implemen-
/
MPC556
NOTES:
Floating-point multiply
Floating-point divide
1. Refer to
Instruction Type
Integer load/store
Integer multiply
Manual (RCPURM/AD)
add or subtract
Floating-point
Floating-point
Integer divide
multiply-add
Table 3-22 Instruction Latency and Blockage
Section 7 Instruction Timing,
CENTRAL PROCESSING UNIT
Rev. 15 October 2000
for details.
Precision
Double
Double
Double
Double
Single
Single
Single
Single
—
—
—
See note
Latency
2 to 11
17
10
7
6
4
4
5
4
2
in the
1
1
RCPU Reference
See note
Blockage
2 to 11
1 or 2
17
10
7
6
4
4
5
4
1
1
1
MOTOROLA
3-38