MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 440

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MPC555
USER’S MANUAL
QCLK EXAMPLES
Example
Number
Figure 13-9
include conversion times based on the following assumption:
Figure 13-9
version in a queue. For other MCU IMB clock frequencies and other input sample
times, the same calculations can be made.
The MCU IMB clock frequency is the basis of the QADC64 timing. The QADC64 re-
quires that the IMB clock frequency be at least twice the QCLK frequency. The QCLK
frequency is established by the combination of the PSH and PSL parameters in
QACR0. The 5-bit PSH field selects the number of IMB clock cycles in the high phase
of the QCLK wave. The 3-bit PSL field selects the number of IMB clock cycles in the
low phase of the QCLK wave.
Example 1 in
twelve cycles of the IMB clock. It also shows that when PSL = 7, the QCLK remains
low for eight IMB clock cycles. In Example 2, PSH = 7, the QCLK remains high for eight
IMB CLOCK
40 MHz EX1
32 MHz EX2
1
2
• Input sample time is as fast as possible (IST = 0, 2 QCLK cycles).
/
F
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
SYS
Frequency
PSA is maintained for software compatibility but has no functional
benefit to this version of the module.
40 MHz
32 MHz
Figure 13-9 QADC64 Clock Programmability Examples
and
and
Control Register 0 Information
Figure 13-9
Table 13-4
Table 13-4
Table 13-4 QADC64 Clock Programmability
PSH
11
7
shows that when PSH = 11, the QCLK remains high for
FQCLK = 1/(250 + 250) = 2 MHz
also show the conversion time calculated for a single con-
show examples of QCLK programmability. The examples
Rev. 15 October 2000
PSA
0
0
NOTE
20 CYCLES
PSL
7
7
Input Sample Time (IST) =%00
QCLK
(MHz)
2.0
2.0
Conversion Time
MOTOROLA
(µs)
QADC64 QCLK EX
7.0
7.0
13-28