MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 380

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.8.2 Memory Controller Status Registers (MSTAT)
10.8.3 Memory Controller Base Registers (BR0 – BR3)
* Reset value is determined by the value on the internal data bus during reset.
** The BR0 Reset value is determined by the value on the internal data bus during reset (reset-configuration word). The
MPC555
USER’S MANUAL
MSTAT — Memory Controller Status Register
BR0 – BR3 — Memory Controller Base Registers 0 – 3 0x2F C100, C108, C110, C118
HARD RESET:
Bit(s)
12:15
MSB
MSB
8:11
reset value of the V bit of BR1-3 = 0.
BA
0:7
16
U
U
0
0
0
17
U
WPER0 –
U
/
1
0
1
WPER3
MPC556
Name
—
—
AT
18
U
U
2
0
2
Reserved
Write protection error for bank x. This bit is asserted when a write-protect error occurs for the
associated memory bank. A bus monitor (responding to TEA assertion) will, if enabled, prompt
the user to read this register if TA is not asserted during a write cycle. WPERx is cleared by writ-
ing one to the bit or by performing a system reset. Writing a zero has no effect on WPER.
Reserved
RESERVED
19
U
U
3
0
3
20
U
4
0
4
ID[4:5]*
Table 10-6 MSTAT Bit Descriptions
PS
21
U
5
0
5
MEMORY CONTROLLER
SERV
Rev. 15 October 2000
RE-
ED
22
U
6
0
6
0
WP
23
U
7
0
7
HRESET
HRESET
0
BA
,
,
WPER
RESERVED
24
U
8
0
0
8
0
Description
WPER
25
U
9
1
0
9
0
WPER
WEBS TBDIP LBDIP SETA
10
10
U
26
2
0
0
WPER
11
11
27
U
3
0
0
12
12
28
U
0
RESERVED
13
13
29
U
0
0
0x2F C178
MOTOROLA
14
14
30
U
BI
0
1
10-28
ID3**
LSB
LSB
15
15
31
U
0
V