MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 234

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

*IRQ0 of the SIPEND register is not affected by the setting or clearing of the IRM0 bit of the SIMASK register. IRQ0 is
6.13.2.3 SIU Interrupt Edge Level Register (SIEL)
6.13.2.4 SIU Interrupt Vector Register
MPC555
USER’S MANUAL
SIEL — SIU Interrupt Edge Level Register
SIVEC — SIU Interrupt Vector
MSB
MSB
a non-maskable interrupt.
ED0
16
16
0
0
0
0
0
0
RESET:
RESET:
RESET:
RESET:
The SIEL is a 32-bit read/write register. Each pair of bits corresponds to an external
interrupt request. The EDx bit, if set, specifies that a falling edge in the corresponding
IRQ line will be detected as an interrupt request. When the EDx bit is 0, a low logical
level in the IRQ line will be detected as an interrupt request. The WMx (wake-up mask)
bit, if set, indicates that an interrupt request detection in the corresponding line causes
the MPC555 / MPC556 to exit low-power mode.
The SIVEC is a 32-bit read-only register that contains an 8-bit code representing the
unmasked interrupt source of the highest priority level. The SIVEC can be read as ei-
ther a byte, half word, or word. When read as a byte, a branch table can be used in
which each entry contains one instruction (branch). When read as a half-word, each
entry can contain a full routine of up to 256 instructions. The interrupt code is defined
such that its two least significant bits are 0, thus allowing indexing into the table.
WM0
17
17
/
0
1
0
0
1
0
MPC556
ED1
18
18
0
2
0
0
2
1
INTERRUPT CODE
WM1
19
19
0
3
0
0
3
1
SYSTEM CONFIGURATION AND PROTECTION
ED2
20
20
0
4
0
0
4
1
WM2
21
21
0
5
0
0
5
1
Rev. 15 October 2000
ED3
22
22
0
6
0
0
6
0
WM3
RESERVED
RESERVED
23
23
0
7
0
0
7
0
ED4
24
24
0
8
0
0
8
0
WM4
25
25
0
9
0
0
9
0
ED5
26
10
26
10
0
0
0
0
WM5
RESERVED
27
11
27
11
0
0
0
0
ED6
28
12
28
12
0
0
0
0
WM6
29
13
29
13
0
0
0
0
0x2F C01C
0x2F C018
MOTOROLA
ED7
30
14
30
14
0
0
0
0
WM7
LSB
LSB
31
15
31
15
6-26
0
0
0
0