MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 516

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14.8.7.6 Receiver Operation
MPC555
USER’S MANUAL
To insert a delimiter between two messages, to place non-listening receivers in wake-
up mode between transmissions, or to signal a re-transmission by forcing an idle-line,
clear and then set TE before data in the serial shifter has shifted out. The transmitter
finishes the transmission, then sends a preamble. After the preamble is transmitted, if
TDRE is set, the transmitter marks idle. Otherwise, normal transmission of the next se-
quence begins.
Both TDRE and TC have associated interrupts. The interrupts are enabled by the
transmit interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits
in SCCxR1. Service routines can load the last data frame in a sequence into SCxDR,
then terminate the transmission when a TDRE interrupt occurs.
Two SCI messages can be separated with minimum idle time by using a preamble of
10 bit-times (11 if a 9-bit data format is specified) of marks (logic ones). Follow these
steps:
In this sequence, if the first data frame of the second message is not transferred to
TDRx prior to the finish of the preamble transmission, then the transmit data line
(TXDx pin) marks idle (logic one) until TDRx is written. In addition, if the last data frame
of the first message finishes shifting out (including the stop bit) and TE is clear, TC
goes high and transmission is considered complete. The TXDx pin reverts to being a
general-purpose output pin.
The receiver can be divided into two segments. The first is the receiver bit processor
logic that synchronizes to the asynchronous receive data and evaluates the logic
sense of each bit in the serial stream. The second receiver segment controls the func-
tional operation and the interface to the CPU including the conversion of the serial data
stream to parallel access by the CPU.
Receiver Bit Processor — The receiver bit processor contains logic to synchronize
the bit-time of the incom-ing data and to evaluate the logic sense of each bit. To ac-
complish this an RT clock, which is 16 times the baud rate, is used to sample each bit.
Each bit-time can thus be divided into 16 time periods called RT1–RT16. The receiver
looks for a possible start bit by watching for a high-to-low transition on the RXDx pin
and by assigning the RT time labels appropriately.
When the receiver is enabled by writing RE in SCCxR1 to one, the receiver bit pro-
cessor logic begins an asynchronous search for a start bit. The goal of this search is
to gain synchronization with a frame. The bit-time synchronization is done at the be-
ginning of each frame so that small differences in the baud rate of the receiver and
transmitter are not cumulative. SCIx also synchronizes on all one-to-zero transitions
1. Write the last data frame of the first message to the TDRx
2. Wait for TDRE to go high, indicating that the last data frame is transferred to the
3. Clear TE and then set TE back to one. This queues the preamble to follow the
4. Write the first data frame of the second message to register TDRx
/
MPC556
transmit serial shifter
stop bit of the current transmission immediately.
QUEUED SERIAL MULTI-CHANNEL MODULE
Rev. 15 October 2000
MOTOROLA
14-54