UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 1007

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Instruction
8-bit data
transfer
Group
2.
3.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an
Mnemonic
MOV
XCH
When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data
access.
When the program memory area is accessed.
Except r = A
instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum.
register (CKC).
A, ES:[HL]
ES:[HL], A
ES:[HL + byte],#byte
A, ES:[HL + byte]
ES:[HL + byte], A
A, ES:[HL + B]
ES:[HL + B], A
A, ES:[HL + C]
ES:[HL + C], A
ES:word[B], #byte
A, ES:word[B]
ES:word[B], A
ES:word[C], #byte
A, ES:word[C]
ES:word[C], A
ES:word[BC], #byte
A, ES:word[BC]
ES:word[BC], A
B, ES:!addr16
C, ES:!addr16
X, ES:!addr16
A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [DE + byte]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
Note 3
1 (r = X)
2 (other
than r = X)
Bytes
Table 29-5. Operation List (3/17)
2
2
4
3
3
3
3
3
3
5
4
4
5
4
4
5
4
4
4
4
4
3
3
4
2
3
2
3
2
2
Note 1 Note 2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
2
Clocks
5
−
−
5
−
5
−
5
−
−
5
−
−
5
−
−
5
−
5
5
5
−
−
−
−
−
−
−
−
−
−
A ← (ES, HL)
(ES, HL) ← A
((ES, HL) + byte) ← byte
A ← ((ES, HL) + byte)
((ES, HL) + byte) ← A
A ← ((ES, HL) + B)
((ES, HL) + B) ← A
A ← ((ES, HL) + C)
((ES, HL) + C) ← A
((ES, B) + word) ← byte
A ← ((ES, B) + word)
((ES, B) + word) ← A
((ES, C) + word) ← byte
A ← ((ES, C) + word)
((ES, C) + word) ← A
((ES, BC) + word) ← byte
A ← ((ES, BC) + word)
((ES, BC) + word) ← A
B ← (ES, addr16)
C ← (ES, addr16)
X ← (ES, addr16)
A ←→ r
A ←→ (saddr)
A ←→ sfr
A ←→ (addr16)
A ←→ (DE)
A ←→ (DE + byte)
A ←→ (HL)
A ←→ (HL + byte)
A ←→ (HL + B)
A ←→ (HL + C)
CPU
) selected by the system clock control
Operation
CHAPTER 29 INSTRUCTION SET
Z AC CY
Flag
1007