UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 933

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
22.1 Functions of Power-on-Clear Circuit
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The power-on-clear circuit (POC) has the following functions.
• Generates internal reset signal at power on.
• Compares supply voltage (V
The reset signal is released when the supply voltage (V
Caution If an internal reset signal is generated in the POC circuit, TRAP, WDRF, INIRF, and LVIRF flags of
Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that
Caution If the low-voltage detector (LVI) is set to ON by an option byte by default, the reset signal is not
V
DD
< V
PDR
released until the supply voltage (V
the reset control flag register (RESF) is cleared.
indicates the reset source is located in the reset control flag register (RESF) for when an internal reset
signal is generated by the watchdog timer (WDT), low-voltage-detector (LVI), or illegal instruction
execution. The RESF register is not cleared to 00H and the flag is set to 1 when an internal reset signal
is generated by WDT or LVI.
For details of the RESF register, see CHAPTER 21 RESET FUNCTION.
.
CHAPTER 22 POWER-ON-CLEAR CIRCUIT
DD
) and detection voltage (V
DD
) exceeds 2.07 V ±0.2 V.
DD
PDR
) exceeds 1.61 V ±0.09 V.
= 1.59 V ±0.09 V), generates internal reset signal when
CHAPTER 22 POWER-ON-CLEAR CIRCUIT
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