UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 724

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Figure 14-98. Example of Contents of Registers for Address Field Transmission of Simplified I
(1) Register setting
SCRmn
SMRmn
SDRmn
SOEm
SOm
(a) Serial mode register mn (SMRmn)
(b) Serial communication operation setting register mn (SCRmn)
(d) Serial output register m (SOm)
(e) Serial output enable register m (SOEm)
Note Serial array unit 0 only.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
Operation clock (f
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
CKSmn
TXEmn
0/1
15
15
15
15
15
0
0
1
2.
CCSmn
RXEmn
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 02, r = 10
78K0R/KF3-L, 78K0R/KG3-L:
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
14
14
14
14
14
0
0
0
0
: Setting is fixed in the CSI master transmission mode,
MCK
DAPmn
13
13
13
13
13
0
0
0
0
) of channel n
Setting of parity bit
00B: No parity
Baud rate setting
CKPmn
12
12
12
12
12
0
0
0
0
11
11
11
11
11
0
0
1
0
CKOm2
EOCmn
0/1
10
10
10
10
10
Note
0
0
0
PTCmn1
CKOm1
Start condition is generated by manipulating the SOmn bit.
SOEmn = 0 until the start condition is generated, and SOEmn =
1 after generation.
Note
0
9
0
9
9
×
0
9
9
PTCmn0
STSmn
CKOm0
0/1
8
0
8
0
8
0
8
8
0
DIRmn
0
0
7
0
7
7
7
7
0
mn = 02, 10, r = 10, 20
SISmn0
0
0
6
6
6
0
0
6
6
Transmit data setting (address + R/W)
SLCmn1
5
1
5
5
0
0
5
5
0
CHAPTER 14 SERIAL ARRAY UNIT
: Setting disabled (set to the initial value)
SLCmn0
SIOr
1
0
4
0
4
4
4
4
0
Operation mode of channel n
Setting of stop bit
01B: Appending 1 bit (ACK)
0
0
1
3
3
3
0
3
3
0: Transfer end interrupt
MDmn2
DLSmn2
SOEm2
SOm2
0/1
0/1
2
1
2
2
1
2
2
MDmn1
DLSmn1
SOEm1
SOm1
2
C (IIC10, IIC20)(1/2)
Note
Note
0
1
1
×
1
1
1
1
×
DLSmn0
MDmn0
SOEm0
SOm0
0/1
0/1
1
0
0
0
0
0
0
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