UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 768

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(3) IICA status register (IICS)
Address: FFF51H
Symbol
This register indicates the status of I
The IICS register is read by a 1-bit or 8-bit memory manipulation instruction only when STT = 1 and during the wait
period.
Reset signal generation clears this register to 00H.
Caution Reading the IICS register while the address match wakeup function is enabled (WUP = 1) in STOP
Remark
IICS
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other
Remark
Condition for clearing (MSTS = 0)
• When a stop condition is detected
• When ALD = 1 (arbitration loss)
• Cleared by LREL = 1 (exit from communications)
• When the IICE bit changes from 1 to 0 (operation
• Reset
Condition for clearing (ALD = 0)
• Automatically cleared after the IICS register is
• When the IICE bit changes from 1 to 0 (operation
• Reset
mode is prohibited. When the WUP bit is changed from 1 to 0 (wakeup operation is stopped),
regardless of the INTIICA interrupt request, the change in status is not reflected until the next
start condition or stop condition is detected. To use the wakeup function, therefore, enable (SPIE
= 1) the interrupt generated by detecting a stop condition and read the IICS register after the
interrupt has been detected.
STT: bit 1 of IICA control register 0 (IICCTL0)
WUP: bit 7 of IICA control register 1 (IICCTL1)
stop)
read
stop)
MSTS
MSTS
ALD
<7>
0
1
0
1
Note
than the IICS register. Therefore, when using the ALD bit, read the data of this bit before the data of
the other bits.
LREL:
IICE:
After reset: 00H
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. The MSTS bit is cleared.
ALD
<6>
Figure 15-7. Format of IICA Status Register (IICS) (1/3)
Bit 7 of IICA control register 0 (IICCTL0)
Bit 6 of IICA control register 0 (IICCTL0)
EXC
<5>
2
C.
R
<4>
COI
Detection of arbitration loss
Master status check flag
TRC
<3>
Condition for setting (MSTS = 1)
• When a start condition is generated
Condition for setting (ALD = 1)
• When the arbitration result is a “loss”.
CHAPTER 15 SERIAL INTERFACE IICA
ACKD
<2>
STD
<1>
SPD
<0>
768