UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 414

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(a) Start timing in interval timer mode
Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> The write data to the TSmn bit is held until count clock generation.
<3> Timer/counter register mn (TCRmn) holds the initial value until count clock generation.
<4> On generation of count clock, the value of timer data register mn (TDRmn) is loaded to the TCRmn
register and count starts.
Start trigger detection signal
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by
setting MDmn0 = 1.
TSmn (write) hold signal
TSmn (write)
Count clock
INTTMmn
TCRmn
Figure 8-15. Start Timing (In Interval Timer Mode)
TEmn
f
CLK
<1>
<2>
Initial value
<3>
CHAPTER 8 TIMER ARRAY UNIT
TDRmn value
When MDmn0 = 1 is set
<4>
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