UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 425

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: FFF3CH
(13) Input switch control register (ISC)
Symbol
ISC
Caution Be sure to clear bits 7 to 3 to “0” in the 78K0R/KC3-L (44-pin, 48-pin), 78K0R/KD3-L, and
Notes 1. 78K0R/KC3-L (44-pin, 48-pin), 78K0R/KD3-L, 78K0R/KE3-L only.
Remarks 1. When the LIN-bus communication function is used, select the input signal of the RxDk pin by setting
The ISC1 and ISC0 bits of the ISC register are used to implement LIN-bus communication operation by using
channel 7 in association with the serial array unit. When the ISC1 bit is set to 1, the input signal of the serial data
input pin (RxDk) is selected as a timer input signal.
The ISC2 bit is set to select the P52/SLTI/SLTO pin as the timer I/O pin of timer channels 0 and 1 (78K0R/KC3-L
(44-pin, 48-pin), 78K0R/KD3-L, 78K0R/KE3-L only).
The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
2. 78K0R/KD3-L and 78K0R/KE3-L only. Only the P52/SLTI/SLTO pin can be assigned to channels 0 and
ISC2
ISC1
ISC0
78K0R/KE3-L. Be sure to clear bits 7 to 2 to “0” in the 78K0R/KC3-L (40-pin).
Be sure to clear bits 7 to 2 to “0” in the 78K0R/KF3-L and 78K0R/KG3-L.
2. 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: k = 0 (RxD0)
0
1
0
1
0
1
1 in the 78K0R/KC3-L (44-pin, 48-pin).
7
0
After reset: 00H
Note 1
ISC1 to 1.
78K0R/KF3-L, 78K0R/KG3-L:
Uses the input signal of the TI07 pin as a timer input (normal operation).
Input signal of the R
width of the sync break field and the pulse width of the sync field).
Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
Uses the input signal of the R
Figure 8-26. Format of Input Switch Control Register (ISC)
P00/TI00
6
0
P52/SLTI
Input Pin
R/W
Note 2
Channel 0
X
5
0
Dk pin is used as timer input (detects the wakeup signal and measures the low
Selecting P52/SLTI/SLTO Pin as Timer I/O Pin
Switching channel 7 input of timer array unit 0
X
Switching external interrupt (INTP0) input
P01/TO00
Dk pin as an external interrupt (wakeup signal detection).
Output Pin
P52/SLTO
4
0
Note 2
k = 3 (RxD3)
3
0
P52/SLTI
Input Pin
CHAPTER 8 TIMER ARRAY UNIT
ISC2
−
2
Note 1
Channel 1
ISC1
1
Output Pin
P52/SLTO
−
ISC0
0
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