UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 341

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note
(Remark is listed on the next page after next.)
Option byte (000C1H)
FRQSEL2,
FRQSEL1
X2/EXCLK
XT2//P124
XT1/P123
X1/P121
Clock operation mode
/P122
This is not mounted onto 44-pin product of the 78K0R/KC3-L.
control register
AMPHS1AMPHS0
(CMC)
AMPH
Crystal/ceramic
oscillation (1 MHz (TYP.))
oscillation (8 MHz (TYP.))
oscillation (20 MHz (TYP.))
External input
Internal high-speed
Internal high-speed
High-speed system
high-speed oscillator
Internal high-speed
oscillation
Subsystem clock
oscillation
Internal high-speed
20 MHz internal
EXCLK OSCSEL
clock oscillator
Crystal
clock
oscillator
oscillator
Clock operation mode
control register
(CMC)
OSCSELS
f
f
f
f
IH20
f
Figure 7-2. Block Diagram of Clock Generator (78K0R/KC3-L (44-pin and 48-pin), 78K0R/KD3-L, 78K0R/KE3-L)
f
EX
IH1
IH8
XT
X
f
f
Clock operation status
MX
f
f
IH
IH20
SUB
control register
Clock operation status
oscillation (30 kHz (TYP.))
Internal low-speed
(CSC)
Internal low-speed
CLS
control register
oscillator
MSTOP
(CSC)
XTSTOP HIOSTOP
STOP mode
signal
f
IL
DSCS
MOST
8
SELDSC
Option byte (000C0H)
WDTON
WDSTBYON
MOST
HALT/STOP mode signal
9
stabilization time counter
OSTS2
MOST
20 MHz internal high-speed
oscillation control register
(DSCCTL)
10
DSCON
X1 oscillation
MOST
Internal bus
OSTS1 OSTS0
11
Internal bus
MOST
3
13
Oscillation stabilization
time counter status
register (OSTC)
Oscillation stabilization
time select register (OSTS)
MOST
15
MOST
17
MOST
18
Main system clock
source selector
TAU0
EN
Peripheral enable
register 2 (PER2)
f
MAIN
CLS
OACMP
Clock output/
buzzer output
EN
CSS
Peripheral enable
register 1 (PER1)
f
f
f
f
f
f
f
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
SUB
/2
/2
/2
/2
/2
/2
MCS
5
4
3
2
Note
MCM0
Watchdog timer
Real-time counter,
clock output/buzzer output
SAU0
EN
1
System clock control
register (CKC)
MD
IV2
EN
and peripheral
IICA
clock source
CPU clock
Note
hardware
selection
4
MD
IV1
ADC
EN
Note
Peripheral enable
register 0 (PER0)
MD
IV0
f
CLK
RTC
EN
Standby controller
operation mode
STOP mode
HALT mode
Normal
CPU
Timer array unit 0
Serial array unit 0
Serial interface IICA
Real-time counter
Programmable gain
amplifier/comparator
A/D converter
Note