UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 474

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
Note 78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
Operation
start
During
operation
Operation
stop
TAU
stop
78K0R/KF3-L, 78K0R/KG3-L:
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
p: Slave channel number
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Note
Sets the TOEmp bit (slave) to 1 (only when operation is
resumed).
The TSmn (master) and TSmp (slave) bits of timer
channel start register m (TSm) are set to 1 at the same
time.
Detects the TImn pin input valid edge of master channel.
Set values of only the CISmn1 and CISmn0 bits of the
TMRmn register can be changed.
Set values of the TMRmp, TDRmn, TDRmp registers,
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be
changed.
The TCRmn and TCRmp registers can always be read.
The TSRmn and TSRmp registers are not used.
Set values of the TOm and TOEm registers can be
changed.
The TTmn (master) and TTmp (slave) bits are set to 1 at
the same time.
The TOEmp bit of slave channel is cleared to 0 and
value is set to the TOmp bit.
To hold the TOmp pin output level
When holding the TOmp pin output level is not
necessary
The TAU0EN and TAU1EN bits of the PER0 and PER2
registers are cleared to 0.
Switches the port mode register to input mode.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
Clears the TOmp bit to 0 after the value to
be held is set to the port register.
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
Figure 8-65. Operation Procedure of One-Shot Pulse Output Function (2/2)
Software Operation
Note
Note
TAU0EN bit of the PER2 register
TAU0EN or TAU1EN bit of the PER0 register
mn = 00, 02, 04, 06, 10, 12
The TEmn and TEmp bits are set to 1 and the master
channel enters the TImn input edge detection wait status.
Master channel starts counting.
Master channel loads the value of the TDRmn register to
timer/counter register mn (TCRmn) when the TImn pin
valid input edge is detected, and the counter starts
counting down. When the count value reaches TCRmn =
0000H, the INTTMmn output is generated, and the counter
stops until the next valid edge is input to the TImn pin.
The slave channel, triggered by INTTMmn of the master
channel, loads the value of the TDRmp register to the
TCRmp register, and the counter starts counting down.
The output level of TOmp becomes active one count clock
after generation of INTTMmn from the master channel. It
becomes inactive when TCRmp = 0000H, and the
counting operation is stopped.
After that, the above operation is repeated.
TEmn, TEmp = 0, and count operation stops.
The TOmp pin outputs the TOmp set level.
The TOmp pin output level is held by port function.
The TOmp pin output level goes into Hi-Z output state.
Power-off status
Counter stops operating.
The TCRmn and TCRmp registers hold count value and
stop.
The TOmp output is not initialized but holds current
status.
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set to
port mode.)
CHAPTER 8 TIMER ARRAY UNIT
Hardware Status
474