UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 348

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(3) Clock operation status control register (CSC)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Note
This register is used to control the operations of the high-speed system clock, internal high-speed oscillation clock,
and subsystem clock
clock).
The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to C0H.
Address: FFFA1H
Symbol
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
CSC
Notes 1.
Cautions 1. After reset release, set the clock operation mode control register (CMC) before
XTSTOP
HIOSTOP
MSTOP
MSTOP
<7>
2.
Figure 7-5. Format of Clock Operation Status Control Register (CSC)
0
1
0
1
0
1
Note
Note 1
After reset: C0H
XTSTOP bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), bit 6 is
The 1 MHz or 8 MHz (TYP.) internal high-speed oscillation clock stops. Stopping the internal
2. To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization
3. When starting XT1 oscillation by setting the XSTOP bit, wait for oscillation of the
4. Do not stop the clock selected for the CPU peripheral hardware clock (f
5. The setting of the flags of the register to stop clock oscillation (invalidate the external
6. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP
fixed to 0.
high-speed oscillator (HIOSTOP = 1) is prohibited while the 20 MHz internal high-speed
oscillation clock is operating (DSCON = 1). Stop the 20 MHz internal high-speed oscillation
clock by using the 20 MHz internal high-speed oscillation control register (DSCCTL) and not
the HIOSTOP bit.
(except the 20 MHz internal high-speed oscillation clock and internal low-speed oscillation
setting the CSC register.
time of the X1 clock by using the oscillation stabilization time counter status register
(OSTC).
subsystem clock to stabilize by setting a wait time using software.
OSC register.
clock input) and the condition before clock oscillation is to be stopped are as Table
7-3.
bit to 0 after releasing reset. Note that if the OSTS register is being used with its
default settings, the OSTS register is not required to be set here.
XTSTOP
X1 oscillator operating
X1 oscillator stopped
XT1 oscillator operating
XT1 oscillator stopped
Internal high-speed oscillator operating
Internal high-speed oscillator stopped
<6>
X1 oscillation mode
Note 1
XT1 oscillation mode
R/W
5
0
Internal high-speed oscillation clock operation control
High-speed system clock operation control
Subsystem clock operation control
External clock from EXCLK
pin is valid
External clock from EXCLK
pin is invalid
4
0
External clock input mode
Note 2
3
0
Input port
CHAPTER 7 CLOCK GENERATOR
2
0
Input port mode
Input port
Input port mode
1
0
HIOSTOP
<0>
CLK
) with the
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