UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 967

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
25.3 Format of On-chip Debug Option Byte
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: 000C3H/010C3H
Address: 000C2H/010C2H
Cautions 1. Be sure to set bits 7 to 3 to “1”.
Note Be sure to set FFH to 000C2H, as these addresses are reserved areas. Also set FFH to 010C2H when the boot
The format of on-chip debug option byte is shown below.
Note Set the same value as 000C3H to 010C3H when the boot swap operation is used because 000C3H is replaced
Caution Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value.
Remark The value on bits 3 to 1 will be written over when the on-chip debug function is in use and thus it will become
swap operation is used because 000C2H is replaced by 010C2H.
by 010C3H.
Be sure to set 000010B to bits 6 to 1.
2.
However, be sure to set the default values (0, 1, and 0) to bits 3 to 1 at setting.
unstable after the setting.
OCDENSET
OCDENSET
software (bit 7 (LVION) of the low-voltage detection register (LVIM) is set to 0), it operates as
follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, the LVION bit will be re-set to 1 when the CPU starts
Even when the LVI default start function is used, if it is set to LVI operation prohibition by the
7
1
7
0
0
1
1
after reset release. There is a period when low-voltage detection cannot be performed normally,
however, when a reset occurs due to WDT and illegal instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
1 is set upon reset occurrence, and the CPU starts operating without waiting for the LVI
stabilization time.
Figure 25-4. Format of On-chip Debug Option Byte (000C3H/010C3H)
Note
Note
OCDERSD
6
1
Figure 25-3. Format of Option Byte (000C2H/010C2H)
6
0
0
1
0
1
Disables on-chip debug operation.
Setting prohibited
Enables on-chip debugging.
Erases data of flash memory in case of failures in authenticating on-chip debug
security ID.
Enables on-chip debugging.
Does not erases data of flash memory in case of failures in authenticating on-chip
debug security ID.
5
1
5
0
4
1
4
0
Control of on-chip debug operation
3
1
3
0
2
1
2
1
CHAPTER 25 OPTION BYTE
1
1
1
0
μ
s max., LVION =
OCDERSD
0
1
0
967