UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 81

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UPD78F1009GB-GAH-AX

Manufacturer Part Number
UPD78F1009GB-GAH-AX
Description
MCU 16BIT 78K0R/KX3-L 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet

Specifications of UPD78F1009GB-GAH-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1009GB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
78K0R/Kx3-L
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Notes 1. TI06/TO06 and TI07/TO07 are shared with P50 and P51, respectively, in products other than the 78K0R/KE3-L.
Remark
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
P00/TI00
P01/TO00
P10/TI02/TO02
P11/TI03/TO03
P12/TI04/TO04/RTCDIV/
RTCCL
P13/TI05/TO05
P14/TI06/TO06
P15/TI07/TO07
P16
P17
P20/ANI0 to P27/ANI7
P30/SO10/TxD1
P31/SI10/RxD1/SDA10/
INTP1
P32/SCK10/SCL10/INTP2
P33
P40/TOOL0
P41/TOOL1
P42
P43
P50/TI06/TO06
P51/TI07/TO07
P52/RTC1HZ/SLTI/SLTO
P53
Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins.
2. P20/ANI0 to P27/ANI7 are set in the digital input port mode after release of reset.
3. TI06/TO06 and TI07/TO07 are shared with P14 and P15, respectively, in the 78K0R/KE3-L.
Pin Name
With products not provided with an EV
Note 1
Note 1
Note 3
Note 3
Note 2
8-R
5-AG
8-R
11-G
5-AG
5-AN
5-AG
8-R
5-AG
8-R
5-AG
I/O Circuit Type
CHAPTER 2 PIN FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
Table 2-3. Connection of Unused Pins (1/3)
I/O
DD
I/O
or EV
SS
Input:
Output: Leave open.
Input:
Output: Leave open.
Input:
Output: Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
Input:
Output: Leave open.
<When on-chip debugging is enabled>
Pull this pin up (pulling it down is prohibited).
<When on-chip debugging is disabled>
Input:
Output: Leave open.
Input:
Output: Leave open.
pin, replace EV
Independently connect to EV
Independently connect to EV
Independently connect to EV
Independently connect to AV
Independently connect to EV
Independently connect to EV
Recommended Connection of Unused Pins
DD
with V
DD
, or replace EV
DD
DD
DD
REF
DD
DD
or EV
or EV
or EV
or EV
or EV
or AV
SS
SS
SS
SS
SS
SS
via a resistor.
via a resistor.
SS
via a resistor.
via a resistor.
via a resistor.
via a resistor.
with V
SS
.
81

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