UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 868

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
17.6 Cautions on Using DMA Controller
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) Priority of DMA
(2) DMA response time
(3) Operation in standby mode
During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending
DMA transfer is started after the ongoing DMA transfer is completed. If two DMA requests are generated at the
same time, however, DMA channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes precedence,
and then interrupt servicing is executed.
The response time of DMA transfer is as follows.
The DMA controller operates as follows in the standby mode.
HALT mode
STOP mode
Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles.
Cautions 1. The above response time does not include the two clock cycles required for a DMA
Remark
Response time
Status
2. When executing a DMA pending instruction (see 17.6 (4)), the maximum response
3. Do not specify successive transfer triggers for a channel within a period equal to the
1 clock: 1/f
transfer.
time is extended by the execution time of that instruction to be held pending.
maximum response time plus one clock cycle, because they might be ignored.
Normal operation
Stops operation.
If DMA transfer and STOP instruction execution contend, DMA transfer may be
damaged. Therefore, stop DMA before executing the STOP instruction.
Table 17-3. DMA Operation in Standby Mode
Table 17-2. Response Time of DMA Transfer
CLK
(f
CLK
: CPU clock)
3 clocks
Minimum Time
DMA Operation
10 clocks
CHAPTER 17 DMA CONTROLLER
Maximum Time
Note
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