UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 164

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note
78K0R/Kx3-L
Address Special Function Register (SFR) Name
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
FFFB0H DMA SFR address register 0
FFFB1H DMA SFR address register 1
FFFB2H DMA RAM address register 0L
FFFB3H DMA RAM address register 0H DRA0H
FFFB4H DMA RAM address register 1L
FFFB5H DMA RAM address register 1H DRA1H
FFFB6H DMA byte count register 0L
FFFB7H DMA byte count register 0H
FFFB8H DMA byte count register 1L
FFFB9H DMA byte count register 1H
FFFBAH DMA mode control register 0
FFFBBH DMA mode control register 1
FFFBCH DMA operation control register 0
FFFBDH DMA operation control register 1
FFFBEH Back ground event control
FFFC0H
FFFC2H
FFFC4H
FFFD0H Interrupt request flag register 2L IF2L
FFFD1H Interrupt request flag register 2H IF2H
FFFD4H Interrupt mask flag register 2L
FFFD5H Interrupt mask flag register 2H
FFFD8H Priority specification flag register
FFFD9H Priority specification flag register
FFFDCH Priority specification flag register
FFFDDH Priority specification flag register
FFFE0H Interrupt request flag register 0L IF0L
FFFE1H Interrupt request flag register 0H IF0H
FFFE2H Interrupt request flag register 1L IF1L
FFFE3H Interrupt request flag register 1H IF1H
FFFE4H Interrupt mask flag register 0L
FFFE5H Interrupt mask flag register 0H
Do not directly operate this SFR, because it is to be used in the self programming library.
register
02L
02H
12L
12H
−
−
−
DRA0L
DRA1L
DBC0L
DBC0H
DBC1L
DBC1H
DRC0
DRC1
BECTL
PFCMD
PFS
FLPMC
PR02L
PR02H
PR12L
PR12H
DSA0
DSA1
DMC0
DMC1
MK2L
MK2H
MK0L
MK0H
Symbol
Note
Note
Note
DRA0
DRA1
DBC0
DBC1
IF2
MK2
PR02
PR12
IF0
IF1
MK0
Table 4-5. SFR List (5/6)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
−
−
−
Manipulable Bit Range
1-bit
−
−
−
−
−
−
−
−
−
−
√
√
√
√
√
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
8-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16-bit
−
−
√
√
√
√
−
−
−
−
−
−
−
−
√
√
√
√
√
√
√
CHAPTER 4 CPU ARCHITECTURE
After Reset
Undefined
Undefined
Undefined
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
164
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√