UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 313

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
6.2.15 Port 14
Notes 1. PCLBUZ/INTP7 is shared with P55, in the 78K0R/KF3-L.
mode register 14 (PM14). When the P140 to P145 pins are used as an input port, use of an on-chip pull-up resistor can
be specified in 1-bit units by pull-up resistor option register 14 (PU14).
port input mode register 14 (PIM14).
output mode register 14 (POM14).
and clock I/O.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
P142/SCK20/SCL20
P143/SI20/RxD2/SDA20
P144/SO20/TxD2
P145/TI07/TO07
Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port
Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
Output from the P142 to P144 pins can be specified as N-ch open-drain output (V
This port can also be used for timer I/O, external interrupt request input, clock/buzzer output, serial interface data I/O,
Reset signal generation sets port 14 to input mode.
Figures 6-47 to 6-50 show block diagrams of port 14.
Cautions 1. To use P142/SCK20/SCL20, P143/SI20/RxD2/SDA20, or P144/SO20/TxD2 as a general-purpose
2. TI07/TO07 is shared with P54, in the 78K0R/KF3-L.
2. To use P145/TI07/TO07 as a general-purpose port, set bit 7 (TO07) of timer output register 0 (TO0)
3. To use P140/PCLBUZ0/INTP6 or P141/PCLBUZ1/INTP7 as a general-purpose port, set bit 7 of
port, note the serial array unit 1 setting. For details, refer to the following tables.
and bit 7 (TOE07) of timer output enable register 0 (TOE0) to “0”, which is the same as their
default status setting.
clock output select registers 0 and 1 (CKS0, CKS1) to “0”, which is the same as their default
status settings.
• Table 14-13 Relationship Between Register Settings and Pins (Channel 0 of Unit 1: CSI20,
• Table 14-14 Relationship Between Register Settings and Pins (Channel 1 of Unit 1: UART2
UART2 Transmission, IIC20)
Reception)
(
μ PD78F10xx: xx = 10 to 12, 27,28)
78K0R/KF3-L
−
−
Note 2
Note 1
√
√
√
√
CHAPTER 6 PORT FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
(
μ PD78F10xx: xx = 13, 14, 29, 30)
78K0R/KG3-L
√
√
√
√
√
√
DD
tolerance) in 1-bit units using port
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