UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 576

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
13.6 Cautions for A/D Converter
(1) Operating current in STOP mode
(2) Input range of ANI0 to ANI15 pins
(3) Conflicting operations
(4) Noise countermeasures
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of the A/D converter mode register
(ADM) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM register to 0 at the same time.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start
operation.
Observe the rated range of the ANI0 to ANI15 pins input voltage. If a voltage of AV
(even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that
channel becomes undefined. In addition, the converted values of the other channels may also be affected.
<1> Conflict between the A/D conversion result register (ADCR, ADCRH) write and the ADCR or ADCRH register
<2> Conflict between the ADCR or ADCRH register write and the A/D converter mode register (ADM) write, the
To maintain the 10-bit resolution, attention must be paid to noise input to the AV
<1> Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply.
<2> The higher the output impedance of the analog input source, the greater the influence. To reduce the noise,
<3> Do not switch these pins with other pins during conversion.
<4> The accuracy is improved if the HALT mode is set immediately after the start of conversion.
Remark ANI0 to ANI9: 78K0R/KC3-L (40-pin, 44-pin)
read by instruction upon the end of conversion
The ADCR or ADCRH register read has priority. After the read operation, the new conversion result is written to
the ADCR or ADCRH registers.
analog input channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end
of conversion
The ADM, ADS, or ADPC registers write has priority. The ADCR or ADCRH register write is not performed, nor
is the conversion end interrupt signal (INTAD) generated.
connecting external C as shown in Figure 13-22 is recommended.
ANI0 to ANI10: 78K0R/KC3-L (48-pin) and 78K0R/KD3-L
ANI0 to ANI11: 78K0R/KE3-L, 78K0R/KF3-L
ANI0 to ANI15: 78K0R/KG3-L
CHAPTER 13 A/D CONVERTER
REF
pin and ANI0 to ANI15 pins.
REF
or higher and AV
SS
or lower
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