UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 690

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
14.6.1 UART transmission
synchronization).
Notes 1. 78K0R/KF3-L, 78K0R/KG3-L only.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Remarks 1. f
UART transmission is an operation to transmit data from the 78K0R/Kx3-L to another device asynchronously (start-stop
Of two channels used for UART, the even channel is used for UART transmission.
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
2. UART4 is only mounted in the 78K0R/KF3-L (
3. Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
UART
78F1030).
specifications (see CHAPTER 30
78K0R/KE3-L), CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)).
2. m: Unit number (m = 0 to 2), n: Channel number (n = 0, 2)
f
78K0R/KG3-L (
78K0R/KG3-L (
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L (
78K0R/KF3-L (
MCK
CLK
:
:
Operation clock frequency of target channel
System clock frequency
TxD0
INTST0
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
None
5, 7, or 8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
Channel 0 of
μ
μ
μ
μ
PD78F1027, 78F1028):
PD78F1013, 78F1014):
PD78F1029, 78F1030):
UART0
PD78F1010, 78F1011, 78F1012): mn = 00, 02, 10, 12
MCK
SAU0
/6 [bps] (SDRmn [15:9] = 2 or more), Min. f
TxD1
INTST1
Channel 2 of
UART1
SAU0
ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L,
μ
PD78F1027, 78F1028) and 78K0R/KG3-L (
TxD2
INTST2
Channel 0 of
UART2
mn = 00, 02
mn = 00, 02, 10,12, 20
mn = 00, 02, 10, 12
mn = 00, 02, 10,12, 20
SAU1
CLK
Note 1
/(2 × 2
CHAPTER 14 SERIAL ARRAY UNIT
11
× 128) [bps]
TxD3
INTST3
Channel 2 of
UART3
SAU1
Note 1
Note 3
TxD4
INTST4
Channel 0 of
UART4
μ
SAU2
PD78F1029,
Note 2
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