UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 623

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
14.4.1 Stopping the operation by units
Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise.
PD78F1010, 78F1011, 78F1012) and 78K0R/KG3-L (
clear bit 3 (SAU1EN) of the PER0 register to 0.
operation of serial array unit 2, clear bit 0 (SAU2EN) of the PER1 register to 0.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The stopping of the operation by units is set by using peripheral enable registers 0 and 1 (PER0, PER1).
The PER0 register and the PER1 register are used to enable or disable supplying the clock to the peripheral hardware.
To stop the operation of serial array unit 0, clear bit 2 (SAU0EN) of the PER0 register to 0. In the 78K0R/KF3-L (
Furthermore, in the 78K0R/KF3-L (
PER0
PER1
Cautions 1. If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and, even if the
Notes 1.
(Caution 2 and Remark is listed on the next page.)
Figure 14-26. Peripheral Enable Register 0 (PER0) Setting When Stopping the Operation by Units
(a) Peripheral enable register 0 (PER0) … Set only the bit of SAUm to be stopped to 0.
(b) Peripheral enable register 1 (PER1) … Set only the bit of SAU2 to be stopped to 0.
2.
3.
RTCEN
×
That is not provided in 40-pin product of the 78K0R/KC3-L.
That is not provided in 40-pin and 44-pin products of the 78K0R/KC3-L.
78K0R/KF3-L and 78K0R/KG3-L only.
0
7
7
Note 1
register is read, only the default value is read
Note that this does not apply to the following registers.
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L (
78K0R/KF3-L (
ISC, NFEN0, PIM3, PIM7, POM3, POM7, PM3, PM7, P3, and P7 registers.
ISC, NFEN0, PIM0, PIM1, PIM14, POM0, POM1, POM14, PM0, PM1, PM4, PM14, P0, P1, P4,
and P14 registers.
ISC, NFEN0, PIM0, PIM1, PIM14, POM0, POM1, POM14, PM0, PM1, PM4, PM5, PM14, P0, P1,
P4, P5, and P14 registers.
0
0
6
6
μ
μ
Control of SAUm input clock
0: Stops supply of input clock
1: Supplies input clock
μ
PD78F1010, 78F1011, 78F1012), 78K0R/KG3-L (
PD78F1027, 78F1028), 78K0R/KG3-L (
PD78F1027, 78F1028) and 78K0R/KG3-L (
ADCEN
×
0
5
5
IICAEN
μ
PD78F1013, 78F1014), to stop the operation of serial array unit 1,
×
0
4
4
Note 2
SAU1EN
0/1
0
3
3
0: Stops supply of input clock
Note 3
Control of SAU2 input clock
1: Supplies input clock
SAU0EN
CHAPTER 14 SERIAL ARRAY UNIT
μ
0/1
PD78F1029, 78F1030):
2
2
0
μ
PD78F1029, 78F1030), to stop the
μ
TAU1EN
PD78F1013, 78F1014):
1
×
1
0
Note 3
TAU0EN
SAU2EN
0/1
0
×
0
Note 3
623
μ