UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 374

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
7.6.5 Example of setting XT1 oscillation clock (products other than 78K0R/KC3-L (40-pin))
oscillation clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start oscillation by
using the operation speed mode control register (OSMC), clock operation mode control register (CMC), and clock
operation status control register (CSC), set the XT1 oscillation clock to f
(CKC).
byte.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
<4> Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize.
<5> Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock.
After a reset release, the CPU/peripheral hardware clock (f
Set the frequency of the internal oscillation clock to be supplied immediately after releasing reset by using the option
[Option byte setting]
Set address 000C1H to FBH.
[Register settings] Set the register in the order of <1> to <5> below.
<1> Use the OSMC register to set the frequency of the CPU/peripheral hardware.
<2> Set (1) the OSCSELS bit of the CMC register to operate the XT1 oscillator.
Note
Example: Wait until the bits reach the following values when a wait of at least 102.4
Use the MDIV2 to MDIV0 bits to specify the division ratio.
(000C1H)
OSMC
Option
OSTC
CMC
CKC
byte
CLS bit is not provided in the 78K0R/KC3-L (40-pin). In the 78K0R/KC3-L (40-pin), bit 7 is fixed to 0.
LVIOFF bit: Set this bit to 0 to turn on the LVI by default when releasing the power-on-reset.
FRQSEL2 and FRQSEL1 bits: Set the FRQSEL2 and FRQSEL1 bits to 1 and 0, respectively, to set the
RTCLPC bit: Set this bit to 1 to operate only the watch in sub-HALT mode (ultra-low current consumption).
AMPHS0 and AMPHS1 bits: These bits are used to specify the oscillation mode of the XT1 oscillator.
resonator.
RTCLPC
MOST8
EXCLK
CLS
7
1
7
0
7
1
7
0
7
0
Note
OSCSEL
MOST9
CSS
6
1
6
0
6
1
6
0
6
0
MOST10
MCS
internal oscillation clock frequency to 1 MHz.
1
0
1
0
0
5
5
5
5
5
OSCSELS
MOST11
MCM0
4
0
4
1
4
1
4
4
0
1
CLK
) always starts operating with the internal high-speed
MOST13
3
3
0
3
1
1
3
0
3
0
CLK
by using the system clock control register
CHAPTER 7 CLOCK GENERATOR
FRQSEL2
AMPHS1
MOST15
MDIV2
0/1
0/1
2
2
0
2
0
2
0
2
FRQSEL1
μ
MOST17
AMPHS0
MDIV1
s is set based on a 10 MHz
FLPC
0/1
0/1
1
0
1
1
1
1
0
1
MOST18
LVIOFF
MDIV0
AMPH
FSEL
0/1
0
0
0
0
1
0
0
0
0
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