UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 1164

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Current
Version
(U20024E)
1st edition
Edition
Change of Figure 13-5. A/D Converter Sampling and A/D Conversion Timing
Change of Figure 13-12. Basic Operation of A/D Converter
Change of Figure 13-14. Example of Select Mode Operation Timing
Change of Figure 13-15. Example of Scan Mode Operation Timing
Addition of 13.6 (12) Starting the A/D converter
Addition of Caution to 14.3 (5) Higher 7 bits of the serial data register mn
(SDRmn)
Change of 14.5.2 Master reception
Change of Figure 14-35. Example of Contents of Registers for Master Reception
of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) (1/2)
Addition of 14.5.2 (4) Processing flow (in continuous reception mode)
Addition of Caution to Figure 14-65. Example of Contents of Registers for Slave
Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) (1/2)
Addition of Caution to Figure 14-66. Initial Setting Procedure for Slave
Transmission/Reception
Addition of Caution to Figure 14-68. Procedure for Resuming Slave
Transmission/Reception
Addition of Caution to Figure 14-70. Flowchart of Slave Transmission/Reception
(in Single- Transmission/Reception Mode)
Addition of Caution to Figure 14-72. Flowchart of Slave Transmission/Reception
(in Continuous Transmission/Reception Mode)
Change of 14.8 Operation of Simplified I2C (IIC10, IIC20) Communication
Change of 14.8.1 Address field transmission
Change of 14.8.2 Data transmission
Change of 14.8.3 Data reception
Addition of Caution, and Change of Remark of 14.8.5 Calculating transfer rate
Addition of Figure 14-109. Processing Procedure in Case of Overrun Error
Change of 15.6 Timing Charts
Addition of Note to Figure 17-4. Format of DMA Mode Control Register n (DMCn)
(1/2)
Change of description in Figure 17-7. Example of Setting for CSI Consecutive
Transmission
Addition of description to 17.5.4 Holding DMA transfer pending by DWAITn bit
Change of Caution in 17-11. Forced Termination of DMA Transfer (2/2)
Change of Caution 2 in 17.6 (2) DMA response time
Change of 17.6 (4) DMA pending instruction
Change of 18.5.4 Interrupt request hold
Change of Figure 20-4. HALT Mode Release by Reset
Change of Figure 20-5. STOP Mode Release by Interrupt Request Generation
Change of Figure 20-6. STOP Mode Release by Reset
Description
APPENDIX B REVISION HISTORY
CHAPTER 13 A/D
CONVERTER
CHAPTER 14 SERIAL
ARRAY UNIT
CHAPTER 15 SERIAL
INTERFACE IICA
CHAPTER 17 DMA
CONTROLLER
CHAPTER 18
INTERRUPT
FUNCTIONS
CHAPTER 20 STANDBY
FUNCTION
Chapter
(2/6)
1164