UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 380

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(6) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D) (products other
(7) CPU clock changing from internal high-speed oscillation clock (B) to 20 MHz internal high-speed oscillation
(8) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(B) → (D)
Status Transition
(B) → (J)
Status Transition
Status Transition
(C) → (B)
than 78K0R/KC3-L (40-pin))
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
clock (J)
Note
Remark (A) to (K) in Table 7-4 correspond to (A) to (K) in Figure 7-19.
instruction after reset release.
(Setting sequence of SFR registers)
Check that V
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Setting Flag of SFR Register
Setting Flag of SFR Register
Table 7-4. CPU Clock Transition and SFR Register Setting Examples (3/6)
DD
≥ 2.7 V and set DSCON = 1.
Unnecessary if the CPU is operating with the 20 MHz
CMC Register
CPU is operating with
DSCCTL Register
Unnecessary if the
the internal high-
speed oscillation
OSCSELS
CSC Register
HIOSTOP
internal high-speed oscillation clock
DSCON
1
clock
Unnecessary if the CPU is operating
0
1
Note
with the subsystem clock
Note
CSC Register
XTSTOP
Waiting for Oscillation
0
Oscillation accuracy
Necessary (100
stabilization time
Stabilization
10
CHAPTER 7 CLOCK GENERATOR
μ
s
Stabilization
Waiting for
Necessary
Oscillation
μ
s)
DSCCTL Register
CKC Register
SELDSC
MCM0
CKC Register
0
1
CSS
1
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