UPD78F1009GB-GAH-AX Renesas Electronics America, UPD78F1009GB-GAH-AX Datasheet - Page 509

• Manufacturer Part Number: UPD78F1009GB-GAH-AX
• Description: MCU 16BIT 78K0R/KX3-L 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1009GB-GAH-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
9.4 Real-Time Counter Operation
9.4.1 Starting operation of real-time counter
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Notes 1. First set the RTCEN bit to 1, while oscillation of the subsystem clock (f
2. Set up the SUBCUD register only if the watch error must be corrected. For details about how to
3. Confirm the procedure described in 9.4.2 Shifting to STOP mode after starting operation when
calculate the correction value, see 9.4.8 Example of watch error correction of real-time counter.
shifting to STOP mode without waiting for INTRTC = 1 after RTCE = 1.
Figure 9-18. Procedure for Starting Operation of Real-Time Counter
No
Setting SEC (clearing RSUBC)
Clearing MK flags of interrupt
Clearing IF flags of interrupt
Setting AMPM, CT2 to CT0
Setting SUBCUD
Reading counter
RTCEN = 1
Setting MONTH
Setting HOUR
Setting WEEK
RTCE = 1
Setting YEAR
INTRTC = 1?
Setting DAY
Setting MIN
RTCE = 0
Start
Yes
Note 3
Note 1
Note 2
Supplies input clock.
Stops counter operation.
Selects 12-/24-hour system and interrupt (INTRTC).
Sets second count register.
Sets minute count register.
Sets hour count register.
Sets week count register.
Sets day count register.
Sets month count register.
Sets year count register.
Sets watch error correction register.
Clears interrupt request flags (RTCIF, RTCIIF).
Clears interrupt mask flags (RTCMK, RTCIMK).
Starts counter operation.
CHAPTER 9 REAL-TIME COUNTER
SUB
) is stable.
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